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![Madalin Bucur](/assets/img/avatar_default.png)
Introduce the QorIQ DPAA 1 Frame Manager interfaces nodes in the P4080DS device tree. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
208 lines
3.4 KiB
Plaintext
208 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P4080DS Device Tree Source
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*
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* Copyright 2011 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019-2020 NXP
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*/
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/include/ "p4080.dtsi"
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/ {
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model = "fsl,P4080DS";
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compatible = "fsl,P4080DS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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phy_rgmii = &phyrgmii;
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phy5_slot3 = &phy5slot3;
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phy6_slot3 = &phy6slot3;
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phy7_slot3 = &phy7slot3;
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phy8_slot3 = &phy8slot3;
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emi1_slot3 = &p4080mdio2;
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emi1_slot4 = &p4080mdio1;
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emi1_slot5 = &p4080mdio3;
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emi1_rgmii = &p4080mdio0;
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emi2_slot4 = &p4080xmdio1;
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emi2_slot5 = &p4080xmdio3;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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fman@400000 {
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ethernet@e0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&phy1>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&phy2>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&phy3>;
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phy-connection-type = "sgmii";
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};
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ethernet@f0000 {
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phy-handle = <&phy10>;
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phy-connection-type = "xgmii";
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};
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};
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fman@500000 {
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ethernet@e0000 {
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phy-handle = <&phy5>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&phy6>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&phy7>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&phy8>;
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phy-connection-type = "sgmii";
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};
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ethernet@f0000 {
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phy-handle = <&phy11>;
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phy-connection-type = "xgmii";
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};
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};
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};
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mdio-mux-emi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-gpio", "mdio-mux";
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mdio-parent-bus = <&mdio0>;
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gpios = <&gpio0 1 0>, <&gpio0 0 0>;
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p4080mdio0: mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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phyrgmii: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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p4080mdio1: mdio@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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phy5: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy6: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy7: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy8: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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p4080mdio2: mdio@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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status = "disabled";
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phy5slot3: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy6slot3: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy7slot3: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy8slot3: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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p4080mdio3: mdio@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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phy0: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy1: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy2: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy3: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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mdio-mux-emi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-gpio", "mdio-mux";
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mdio-parent-bus = <&xmdio0>;
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gpios = <&gpio0 3 0>, <&gpio0 2 0>;
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p4080xmdio1: mdio@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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phy11: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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p4080xmdio3: mdio@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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phy10: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x4>;
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};
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};
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};
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};
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/include/ "p4080si-post.dtsi"
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