mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
e721b882e9
Separate the ability to define tests and assert status of test functions from the dm tests so they can be used more consistently throughout all tests. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
225 lines
7.2 KiB
C
225 lines
7.2 KiB
C
/*
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* Copyright (C) 2013 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Note: Test coverage does not include 10-bit addressing
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <asm/state.h>
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#include <asm/test.h>
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#include <dm/device-internal.h>
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#include <dm/test.h>
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#include <dm/uclass-internal.h>
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#include <dm/util.h>
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#include <test/ut.h>
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static const int busnum;
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static const int chip = 0x2c;
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/* Test that we can find buses and chips */
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static int dm_test_i2c_find(struct unit_test_state *uts)
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{
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struct udevice *bus, *dev;
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const int no_chip = 0x10;
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ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_I2C, busnum,
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false, &bus));
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/*
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* i2c_post_bind() will bind devices to chip selects. Check this then
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* remove the emulation and the slave device.
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*/
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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ut_assertok(dm_i2c_probe(bus, chip, 0, &dev));
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ut_asserteq(-ENODEV, dm_i2c_probe(bus, no_chip, 0, &dev));
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ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_I2C, 1, &bus));
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return 0;
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}
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DM_TEST(dm_test_i2c_find, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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static int dm_test_i2c_read_write(struct unit_test_state *uts)
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{
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struct udevice *bus, *dev;
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uint8_t buf[5];
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
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ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\0AB\0", sizeof(buf)));
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return 0;
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}
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DM_TEST(dm_test_i2c_read_write, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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static int dm_test_i2c_speed(struct unit_test_state *uts)
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{
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struct udevice *bus, *dev;
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uint8_t buf[5];
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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/* Use test mode so we create the required errors for invalid speeds */
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sandbox_i2c_set_test_mode(bus, true);
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ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
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ut_assertok(dm_i2c_set_bus_speed(bus, 100000));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(dm_i2c_set_bus_speed(bus, 400000));
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ut_asserteq(400000, dm_i2c_get_bus_speed(bus));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5));
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sandbox_i2c_set_test_mode(bus, false);
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return 0;
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}
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DM_TEST(dm_test_i2c_speed, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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static int dm_test_i2c_offset_len(struct unit_test_state *uts)
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{
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struct udevice *bus, *dev;
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uint8_t buf[5];
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
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ut_assertok(i2c_set_chip_offset_len(dev, 1));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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/* This is not supported by the uclass */
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ut_asserteq(-EINVAL, i2c_set_chip_offset_len(dev, 5));
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return 0;
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}
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DM_TEST(dm_test_i2c_offset_len, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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static int dm_test_i2c_probe_empty(struct unit_test_state *uts)
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{
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struct udevice *bus, *dev;
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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/* Use test mode so that this chip address will always probe */
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sandbox_i2c_set_test_mode(bus, true);
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ut_assertok(dm_i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev));
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sandbox_i2c_set_test_mode(bus, false);
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return 0;
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}
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DM_TEST(dm_test_i2c_probe_empty, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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static int dm_test_i2c_bytewise(struct unit_test_state *uts)
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{
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struct udevice *bus, *dev;
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struct udevice *eeprom;
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uint8_t buf[5];
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
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/* Tell the EEPROM to only read/write one register at a time */
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ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
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ut_assertnonnull(eeprom);
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sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_SINGLE_BYTE);
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/* Now we only get the first byte - the rest will be 0xff */
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
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/* If we do a separate transaction for each byte, it works */
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ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
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/* This will only write A */
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ut_assertok(i2c_set_chip_flags(dev, 0));
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ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
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/* Check that the B was ignored */
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ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\0A\0\0\0", sizeof(buf)));
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/* Now write it again with the new flags, it should work */
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ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS));
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ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
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ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS |
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DM_I2C_CHIP_RD_ADDRESS));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "\0\0AB\0\0", sizeof(buf)));
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/* Restore defaults */
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sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_NONE);
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ut_assertok(i2c_set_chip_flags(dev, 0));
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return 0;
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}
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DM_TEST(dm_test_i2c_bytewise, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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static int dm_test_i2c_offset(struct unit_test_state *uts)
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{
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struct udevice *eeprom;
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struct udevice *dev;
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uint8_t buf[5];
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ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev));
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/* Do a transfer so we can find the emulator */
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
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/* Offset length 0 */
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sandbox_i2c_eeprom_set_offset_len(eeprom, 0);
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ut_assertok(i2c_set_chip_offset_len(dev, 0));
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ut_assertok(dm_i2c_write(dev, 10 /* ignored */, (uint8_t *)"AB", 2));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "AB\0\0\0\0", sizeof(buf)));
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/* Offset length 1 */
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sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
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ut_assertok(i2c_set_chip_offset_len(dev, 1));
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ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(memcmp(buf, "ABAB\0", sizeof(buf)));
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/* Offset length 2 */
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sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
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ut_assertok(i2c_set_chip_offset_len(dev, 2));
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ut_assertok(dm_i2c_write(dev, 0x210, (uint8_t *)"AB", 2));
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ut_assertok(dm_i2c_read(dev, 0x210, buf, 5));
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ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
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/* Offset length 3 */
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sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
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ut_assertok(i2c_set_chip_offset_len(dev, 2));
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ut_assertok(dm_i2c_write(dev, 0x410, (uint8_t *)"AB", 2));
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ut_assertok(dm_i2c_read(dev, 0x410, buf, 5));
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ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
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/* Offset length 4 */
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sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
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ut_assertok(i2c_set_chip_offset_len(dev, 2));
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ut_assertok(dm_i2c_write(dev, 0x420, (uint8_t *)"AB", 2));
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ut_assertok(dm_i2c_read(dev, 0x420, buf, 5));
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ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
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/* Restore defaults */
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sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
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return 0;
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}
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DM_TEST(dm_test_i2c_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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