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https://github.com/brain-hackers/u-boot-brain
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c68721d93a
By default the device control module registers are locked, preventing any writes to its registers. Unlock those registers as part of the init flow. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: Architecture initialization
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*
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* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <spl.h>
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#include <asm/arch/hardware.h>
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#ifdef CONFIG_SPL_BUILD
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static void mmr_unlock(u32 base, u32 partition)
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{
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/* Translate the base address */
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phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
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/* Unlock the requested partition if locked using two-step sequence */
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writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
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writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
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}
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static void ctrl_mmr_unlock(void)
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{
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/* Unlock all WKUP_CTRL_MMR0 module registers */
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
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/* Unlock all MCU_CTRL_MMR0 module registers */
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mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
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/* Unlock all CTRL_MMR0 module registers */
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mmr_unlock(CTRL_MMR0_BASE, 0);
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mmr_unlock(CTRL_MMR0_BASE, 1);
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mmr_unlock(CTRL_MMR0_BASE, 2);
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mmr_unlock(CTRL_MMR0_BASE, 3);
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mmr_unlock(CTRL_MMR0_BASE, 6);
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mmr_unlock(CTRL_MMR0_BASE, 7);
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}
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static void store_boot_index_from_rom(void)
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{
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u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL;
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*boot_index = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
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}
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void board_init_f(ulong dummy)
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{
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/*
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* Cannot delay this further as there is a chance that
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* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
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*/
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store_boot_index_from_rom();
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/* Make all control module registers accessible */
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ctrl_mmr_unlock();
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/* Init DM early in-order to invoke system controller */
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spl_early_init();
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/* Prepare console output */
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preloader_console_init();
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}
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static u32 __get_backup_bootmedia(u32 devstat)
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{
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u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
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CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
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switch (bkup_boot) {
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case BACKUP_BOOT_DEVICE_USB:
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return BOOT_DEVICE_USB;
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case BACKUP_BOOT_DEVICE_UART:
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return BOOT_DEVICE_UART;
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case BACKUP_BOOT_DEVICE_ETHERNET:
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return BOOT_DEVICE_ETHERNET;
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case BACKUP_BOOT_DEVICE_MMC2:
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return BOOT_DEVICE_MMC2;
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case BACKUP_BOOT_DEVICE_SPI:
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return BOOT_DEVICE_SPI;
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case BACKUP_BOOT_DEVICE_HYPERFLASH:
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return BOOT_DEVICE_HYPERFLASH;
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case BACKUP_BOOT_DEVICE_I2C:
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return BOOT_DEVICE_I2C;
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};
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return BOOT_DEVICE_RAM;
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}
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static u32 __get_primary_bootmedia(u32 devstat)
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{
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u32 bootmode = devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK;
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if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
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bootmode = BOOT_DEVICE_SPI;
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return bootmode;
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}
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u32 spl_boot_device(void)
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{
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL);
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if (bootindex == K3_PRIMARY_BOOTMODE)
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return __get_primary_bootmedia(devstat);
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else
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return __get_backup_bootmedia(devstat);
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}
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#endif
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#ifndef CONFIG_SYSRESET
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void reset_cpu(ulong ignored)
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{
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}
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#endif
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