mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
363 lines
9.6 KiB
C
363 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RCar Gen3 CPG MSSR driver
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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#define CPG_RST_MODEMR 0x0060
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#define CPG_PLL0CR 0x00d8
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#define CPG_PLL2CR 0x002c
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#define CPG_PLL4CR 0x01f4
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#define CPG_RPC_PREDIV_MASK 0x3
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#define CPG_RPC_PREDIV_OFFSET 3
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#define CPG_RPC_POSTDIV_MASK 0x7
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#define CPG_RPC_POSTDIV_OFFSET 0
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/*
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* SDn Clock
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*/
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#define CPG_SD_STP_HCK BIT(9)
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#define CPG_SD_STP_CK BIT(8)
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#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
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#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
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#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
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{ \
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.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
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((stp_ck) ? CPG_SD_STP_CK : 0) | \
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((sd_srcfc) << 2) | \
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((sd_fc) << 0), \
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.div = (sd_div), \
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}
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struct sd_div_table {
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u32 val;
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unsigned int div;
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};
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/* SDn divider
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* sd_srcfc sd_fc div
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* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
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*-------------------------------------------------------------------
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* 0 0 0 (1) 1 (4) 4
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* 0 0 1 (2) 1 (4) 8
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* 1 0 2 (4) 1 (4) 16
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* 1 0 3 (8) 1 (4) 32
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* 1 0 4 (16) 1 (4) 64
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* 0 0 0 (1) 0 (2) 2
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* 0 0 1 (2) 0 (2) 4
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* 1 0 2 (4) 0 (2) 8
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* 1 0 3 (8) 0 (2) 16
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* 1 0 4 (16) 0 (2) 32
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*/
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static const struct sd_div_table cpg_sd_div_table[] = {
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/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
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};
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static int gen3_clk_setup_sdif_div(struct clk *clk)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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struct cpg_mssr_info *info = priv->info;
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const struct cpg_core_clk *core;
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struct clk parent;
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int ret;
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ret = renesas_clk_get_parent(clk, info, &parent);
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if (ret) {
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printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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if (renesas_clk_is_mod(&parent))
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return 0;
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ret = renesas_clk_get_core(&parent, info, &core);
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if (ret)
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return ret;
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if (core->type != CLK_TYPE_GEN3_SD)
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return 0;
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debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
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writel(1, priv->base + core->offset);
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return 0;
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}
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static int gen3_clk_enable(struct clk *clk)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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int ret = gen3_clk_setup_sdif_div(clk);
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if (ret)
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return ret;
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return renesas_clk_endisable(clk, priv->base, true);
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}
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static int gen3_clk_disable(struct clk *clk)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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return renesas_clk_endisable(clk, priv->base, false);
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}
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static ulong gen3_clk_get_rate(struct clk *clk)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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struct cpg_mssr_info *info = priv->info;
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struct clk parent;
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const struct cpg_core_clk *core;
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const struct rcar_gen3_cpg_pll_config *pll_config =
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priv->cpg_pll_config;
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u32 value, mult, prediv, postdiv, rate = 0;
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int i, ret;
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debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
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ret = renesas_clk_get_parent(clk, info, &parent);
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if (ret) {
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printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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if (renesas_clk_is_mod(clk)) {
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rate = gen3_clk_get_rate(&parent);
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debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
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__func__, __LINE__, parent.id, rate);
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return rate;
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}
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ret = renesas_clk_get_core(clk, info, &core);
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if (ret)
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return ret;
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switch (core->type) {
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case CLK_TYPE_IN:
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if (core->id == info->clk_extal_id) {
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rate = clk_get_rate(&priv->clk_extal);
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debug("%s[%i] EXTAL clk: rate=%u\n",
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__func__, __LINE__, rate);
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return rate;
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}
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if (core->id == info->clk_extalr_id) {
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rate = clk_get_rate(&priv->clk_extalr);
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debug("%s[%i] EXTALR clk: rate=%u\n",
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__func__, __LINE__, rate);
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return rate;
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}
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return -EINVAL;
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case CLK_TYPE_GEN3_MAIN:
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rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
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debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, pll_config->extal_div, rate);
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return rate;
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case CLK_TYPE_GEN3_PLL0:
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value = readl(priv->base + CPG_PLL0CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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rate = gen3_clk_get_rate(&parent) * mult;
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debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
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__func__, __LINE__, core->parent, mult, rate);
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return rate;
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case CLK_TYPE_GEN3_PLL1:
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rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
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debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, pll_config->pll1_mult, rate);
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return rate;
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case CLK_TYPE_GEN3_PLL2:
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value = readl(priv->base + CPG_PLL2CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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rate = gen3_clk_get_rate(&parent) * mult;
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debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
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__func__, __LINE__, core->parent, mult, rate);
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return rate;
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case CLK_TYPE_GEN3_PLL3:
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rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
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debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, pll_config->pll3_mult, rate);
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return rate;
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case CLK_TYPE_GEN3_PLL4:
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value = readl(priv->base + CPG_PLL4CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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rate = gen3_clk_get_rate(&parent) * mult;
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debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
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__func__, __LINE__, core->parent, mult, rate);
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return rate;
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case CLK_TYPE_FF:
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case CLK_TYPE_GEN3_PE: /* FIXME */
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rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
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debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, core->mult, core->div, rate);
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return rate;
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case CLK_TYPE_GEN3_SD: /* FIXME */
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value = readl(priv->base + core->offset);
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value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
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for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
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if (cpg_sd_div_table[i].val != value)
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continue;
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rate = gen3_clk_get_rate(&parent) /
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cpg_sd_div_table[i].div;
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debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, cpg_sd_div_table[i].div, rate);
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return rate;
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}
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return -EINVAL;
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case CLK_TYPE_GEN3_RPC:
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rate = gen3_clk_get_rate(&parent);
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value = readl(priv->base + core->offset);
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prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
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CPG_RPC_PREDIV_MASK;
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if (prediv == 2)
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rate /= 5;
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else if (prediv == 3)
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rate /= 6;
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else
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return -EINVAL;
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postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
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CPG_RPC_POSTDIV_MASK;
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rate /= postdiv + 1;
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debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, prediv, postdiv, rate);
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return -EINVAL;
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}
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printf("%s[%i] unknown fail\n", __func__, __LINE__);
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return -ENOENT;
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}
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static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
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{
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/* Force correct SD-IF divider configuration if applicable */
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gen3_clk_setup_sdif_div(clk);
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return gen3_clk_get_rate(clk);
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}
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static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
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{
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if (args->args_count != 2) {
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debug("Invaild args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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clk->id = (args->args[0] << 16) | args->args[1];
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return 0;
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}
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const struct clk_ops gen3_clk_ops = {
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.enable = gen3_clk_enable,
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.disable = gen3_clk_disable,
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.get_rate = gen3_clk_get_rate,
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.set_rate = gen3_clk_set_rate,
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.of_xlate = gen3_clk_of_xlate,
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};
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int gen3_clk_probe(struct udevice *dev)
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{
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struct gen3_clk_priv *priv = dev_get_priv(dev);
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struct cpg_mssr_info *info =
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(struct cpg_mssr_info *)dev_get_driver_data(dev);
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fdt_addr_t rst_base;
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u32 cpg_mode;
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int ret;
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priv->base = (struct gen3_base *)devfdt_get_addr(dev);
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if (!priv->base)
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return -EINVAL;
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priv->info = info;
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ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
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if (ret < 0)
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return ret;
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rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
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if (rst_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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cpg_mode = readl(rst_base + CPG_RST_MODEMR);
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priv->cpg_pll_config =
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(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
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if (!priv->cpg_pll_config->extal_div)
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return -EINVAL;
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ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
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if (ret < 0)
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return ret;
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if (info->extalr_node) {
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ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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int gen3_clk_remove(struct udevice *dev)
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{
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struct gen3_clk_priv *priv = dev_get_priv(dev);
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return renesas_clk_remove(priv->base, priv->info);
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}
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