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https://github.com/brain-hackers/u-boot-brain
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8d67c3685e
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. It works in two mode: standalone mode and PCIe endpoint mode. T2080PCIe-RDB Feature Overview ------------------------------ Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus: - NOR: 128MB 16-bit NOR flash - NAND: 512MB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 Crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
72 lines
1.4 KiB
C
72 lines
1.4 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Freescale T2080RDB board-specific CPLD controlling supports.
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*/
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#include <common.h>
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#include <command.h>
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#include "cpld.h"
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u8 cpld_read(unsigned int reg)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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return in_8(p + reg);
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}
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void cpld_write(unsigned int reg, u8 value)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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out_8(p + reg, value);
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}
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/* Set the boot bank to the alternate bank */
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void cpld_set_altbank(void)
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{
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u8 reg = CPLD_READ(flash_csr);
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reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
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CPLD_WRITE(flash_csr, reg);
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CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
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}
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/* Set the boot bank to the default bank */
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void cpld_set_defbank(void)
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{
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u8 reg = CPLD_READ(flash_csr);
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reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
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CPLD_WRITE(flash_csr, reg);
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CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
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}
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int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (strcmp(argv[2], "altbank") == 0)
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cpld_set_altbank();
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else
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cpld_set_defbank();
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} else {
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rc = cmd_usage(cmdtp);
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}
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return rc;
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}
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U_BOOT_CMD(
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cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
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"Reset the board or alternate bank",
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"reset: reset to default bank\n"
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"cpld reset altbank: reset to alternate bank\n"
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);
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