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https://github.com/brain-hackers/u-boot-brain
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337fcdc06b
Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/arch/ccu.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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static struct ccu_clk_gate h6_gates[] = {
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[CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
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[CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
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[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
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[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
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};
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static struct ccu_reset h6_resets[] = {
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[RST_BUS_UART0] = RESET(0x90c, BIT(16)),
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[RST_BUS_UART1] = RESET(0x90c, BIT(17)),
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[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
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[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
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};
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static const struct ccu_desc h6_ccu_desc = {
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.gates = h6_gates,
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.resets = h6_resets,
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};
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static int h6_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(h6_resets));
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}
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static const struct udevice_id h6_ccu_ids[] = {
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{ .compatible = "allwinner,sun50i-h6-ccu",
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.data = (ulong)&h6_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun50i_h6) = {
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.name = "sun50i_h6_ccu",
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.id = UCLASS_CLK,
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.of_match = h6_ccu_ids,
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.priv_auto_alloc_size = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = h6_clk_bind,
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};
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