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https://github.com/brain-hackers/u-boot-brain
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6901aab8e3
Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/arch/ccu.h>
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#include <dt-bindings/clock/sun9i-a80-ccu.h>
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#include <dt-bindings/reset/sun9i-a80-ccu.h>
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static const struct ccu_clk_gate a80_gates[] = {
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[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
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[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
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[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
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[CLK_BUS_UART3] = GATE(0x594, BIT(19)),
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[CLK_BUS_UART4] = GATE(0x594, BIT(20)),
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[CLK_BUS_UART5] = GATE(0x594, BIT(21)),
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};
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static const struct ccu_reset a80_resets[] = {
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[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
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[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
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[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
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[RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
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[RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
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[RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
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};
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static const struct ccu_desc a80_ccu_desc = {
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.gates = a80_gates,
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.resets = a80_resets,
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};
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static int a80_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(a80_resets));
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}
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static const struct udevice_id a80_ccu_ids[] = {
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{ .compatible = "allwinner,sun9i-a80-ccu",
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.data = (ulong)&a80_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun9i_a80) = {
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.name = "sun9i_a80_ccu",
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.id = UCLASS_CLK,
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.of_match = a80_ccu_ids,
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.priv_auto_alloc_size = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = a80_clk_bind,
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};
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