mirror of
https://github.com/brain-hackers/u-boot-brain
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089df18bfe
Commit 94e3c8c4fd ("crypto/fsl - Add progressive hashing support
using hardware acceleration.") created entries for CONFIG_SHA1,
CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
However, no defconfig has migrated to it. Complete the move by first
adding additional logic to various Kconfig files to select this when
required and then use the moveconfig tool. In many cases we can select
these because they are required to implement other drivers. We also
correct how we include the various hashing algorithms in SPL.
This commit was generated as follows (after Kconfig additions):
[1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL
[2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL
Note:
We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously
because there is dependency between them.
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Priyanka Jain <Priyanka.Jain@freescale.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Feng Li <feng.li_2@nxp.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Cc: Mingkai Hu <Mingkai.Hu@freescale.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
144 lines
4.2 KiB
C
144 lines
4.2 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SECURE_BOOT_H
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#define __FSL_SECURE_BOOT_H
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#include <asm/config_mpc85xx.h>
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#ifdef CONFIG_SECURE_BOOT
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#if defined(CONFIG_FSL_CORENET)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
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#elif defined(CONFIG_TARGET_BSC9132QDS)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
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#elif defined(CONFIG_TARGET_C29XPCIE)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
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#else
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#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
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#endif
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#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
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#if defined(CONFIG_TARGET_B4860QDS) || \
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defined(CONFIG_TARGET_B4420QDS) || \
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defined(CONFIG_TARGET_T4160QDS) || \
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defined(CONFIG_TARGET_T4240QDS) || \
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defined(CONFIG_TARGET_T2080QDS) || \
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defined(CONFIG_TARGET_T2080RDB) || \
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defined(CONFIG_TARGET_T1040QDS) || \
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defined(CONFIG_TARGET_T1040RDB) || \
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defined(CONFIG_TARGET_T1040D4RDB) || \
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defined(CONFIG_TARGET_T1042RDB) || \
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defined(CONFIG_TARGET_T1042D4RDB) || \
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defined(CONFIG_TARGET_T1042RDB_PI) || \
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defined(CONFIG_ARCH_T1023) || \
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defined(CONFIG_ARCH_T1024)
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_CPC_REINIT_F
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#endif
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#define CONFIG_KEY_REVOCATION
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#undef CONFIG_SYS_INIT_L3_ADDR
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#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
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#endif
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#if defined(CONFIG_RAMBOOT_PBL)
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#undef CONFIG_SYS_INIT_L3_ADDR
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#ifdef CONFIG_SYS_INIT_L3_VADDR
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#define CONFIG_SYS_INIT_L3_ADDR \
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(CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
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0xbff00000
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#else
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#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
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#endif
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#endif
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#if defined(CONFIG_TARGET_C29XPCIE)
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#define CONFIG_KEY_REVOCATION
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#endif
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#if defined(CONFIG_ARCH_P3041) || \
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defined(CONFIG_ARCH_P4080) || \
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defined(CONFIG_ARCH_P5020) || \
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defined(CONFIG_ARCH_P5040) || \
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defined(CONFIG_ARCH_P2041)
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#define CONFIG_FSL_TRUST_ARCH_v1
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#endif
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#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
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/* The key used for verification of next level images
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* is picked up from an Extension Table which has
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* been verified by the ISBC (Internal Secure boot Code)
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* in boot ROM of the SoC.
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* The feature is only applicable in case of NOR boot and is
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* not applicable in case of RAMBOOT (NAND, SD, SPI).
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*/
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#define CONFIG_FSL_ISBC_KEY_EXT
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#endif
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#endif /* #ifdef CONFIG_SECURE_BOOT */
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#ifdef CONFIG_CHAIN_OF_TRUST
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#ifdef CONFIG_SPL_BUILD
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/*
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* PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
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* due to space crunch on CPC and thus malloc will not work.
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*/
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#define CONFIG_SPL_PPAACT_ADDR 0x2e000000
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#define CONFIG_SPL_SPAACT_ADDR 0x2f000000
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#define CONFIG_SPL_JR0_LIODN_S 454
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#define CONFIG_SPL_JR0_LIODN_NS 458
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/*
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* Define the key hash for U-Boot here if public/private key pair used to
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* sign U-boot are different from the SRK hash put in the fuse
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* Example of defining KEY_HASH is
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* #define CONFIG_SPL_UBOOT_KEY_HASH \
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* "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
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* else leave it defined as NULL
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*/
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#define CONFIG_SPL_UBOOT_KEY_HASH NULL
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#endif /* ifdef CONFIG_SPL_BUILD */
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#define CONFIG_CMD_ESBC_VALIDATE
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#define CONFIG_FSL_SEC_MON
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#ifndef CONFIG_SPL_BUILD
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/*
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* fsl_setenv_chain_of_trust() must be called from
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* board_late_init()
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*/
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/* If Boot Script is not on NOR and is required to be copied on RAM */
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#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
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#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
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#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
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#define CONFIG_BS_HDR_SIZE 0x00002000
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#define CONFIG_BS_ADDR_RAM 0x00012000
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#define CONFIG_BS_ADDR_DEVICE 0x00802000
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#define CONFIG_BS_SIZE 0x00001000
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#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
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#else
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/* The bootscript header address is different for B4860 because the NOR
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* mapping is different on B4 due to reduced NOR size.
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*/
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#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
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#elif defined(CONFIG_FSL_CORENET)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
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#elif defined(CONFIG_TARGET_BSC9132QDS)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
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#elif defined(CONFIG_TARGET_C29XPCIE)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
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#else
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
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#endif
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#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
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#include <config_fsl_chain_trust.h>
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#endif /* #ifndef CONFIG_SPL_BUILD */
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#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
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#endif
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