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https://github.com/brain-hackers/u-boot-brain
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6ad8d67de8
The control module provides options to set various signal integrity parameters like the output impedance, slew rate, load capacitance for different pad groups. Configure these as required for the omap5430 sevm board. Signed-off-by: R Sricharan <r.sricharan@ti.com>
304 lines
9.4 KiB
C
304 lines
9.4 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Authors:
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* Aneesh V <aneesh@ti.com>
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* Sricharan R <r.sricharan@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP5_H_
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#define _OMAP5_H_
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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/*
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* L4 Peripherals - L4 Wakeup and L4 Core now
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*/
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#define OMAP54XX_L4_CORE_BASE 0x4A000000
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#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
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#define OMAP54XX_L4_PER_BASE 0x48000000
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#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
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#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000
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#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
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#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
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/* CONTROL */
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#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
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#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
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#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800)
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/* LPDDR2 IO regs. To be verified */
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#define LPDDR2_IO_REGS_BASE 0x4A100638
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/* CONTROL_ID_CODE */
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#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
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/* To be verified */
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#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F
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/* STD_FUSE_PROD_ID_1 */
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#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
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#define PROD_ID_1_SILICON_TYPE_SHIFT 16
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#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16)
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/* UART */
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#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
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#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
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#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
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/* General Purpose Timers */
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#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
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#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
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#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
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/* Watchdog Timer2 - MPU watchdog */
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#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
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/* 32KTIMER */
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#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000)
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/* GPMC */
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#define OMAP54XX_GPMC_BASE 0x50000000
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/* SYSTEM CONTROL MODULE */
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#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
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/*
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* Hardware Register Details
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*/
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/* Watchdog Timer */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* GP Timer */
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/*
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* PRCM
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*/
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/* PRM */
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#define PRM_BASE 0x4AE06000
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#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
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#define PRM_RSTCTRL PRM_DEVICE_BASE
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#define PRM_RSTCTRL_RESET 0x01
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/* Control Module */
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#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
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#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
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#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
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#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
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/* LPDDR2 IO regs */
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#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
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#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
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#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
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#define LPDDR2IO_GR10_WD_MASK (3 << 17)
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#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
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/* CONTROL_EFUSE_2 */
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#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
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#define MMC1_PWRDNZ (1 << 26)
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#define MMC1_PBIASLITE_PWRDNZ (1 << 22)
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#define MMC1_PBIASLITE_VMODE (1 << 21)
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#ifndef __ASSEMBLY__
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struct s32ktimer {
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unsigned char res[0x10];
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unsigned int s32k_cr; /* 0x10 */
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};
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#define OMAP5_IOREGS_BASE 0x4A002DA0
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struct omap5_sys_ctrl_regs {
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u32 control_paconf_global; /* 0x4A002DA0 */
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u32 control_paconf_mode; /* 0x4A002DA4 */
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u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
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u32 control_smart1io_padconf_1; /* 0x4A002DAC */
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u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
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u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
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u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
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u32 control_smart2io_padconf_2; /* 0x4A002DBC */
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u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
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u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
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u32 pad1[14];
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u32 control_pbias; /* 0x4A002E00 */
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u32 control_i2c_0; /* 0x4A002E04 */
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u32 control_camera_rx; /* 0x4A002E08 */
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u32 control_hdmi_tx_phy; /* 0x4A002E0C */
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u32 control_uniportm; /* 0x4A002E10 */
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u32 control_dsiphy; /* 0x4A002E14 */
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u32 control_mcbsplp; /* 0x4A002E18 */
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u32 control_usb2phycore; /* 0x4A002E1C */
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u32 control_hdmi_1; /*0x4A002E20*/
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u32 control_hsi; /*0x4A002E24*/
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u32 pad2[2];
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u32 control_ddr3ch1_0; /*0x4A002E30*/
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u32 control_ddr3ch2_0; /*0x4A002E34*/
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u32 control_ddrch1_0; /*0x4A002E38*/
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u32 control_ddrch1_1; /*0x4A002E3C*/
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u32 control_ddrch2_0; /*0x4A002E40*/
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u32 control_ddrch2_1; /*0x4A002E44*/
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u32 control_lpddr2ch1_0; /*0x4A002E48*/
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u32 control_lpddr2ch1_1; /*0x4A002E4C*/
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u32 control_ddrio_0; /*0x4A002E50*/
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u32 control_ddrio_1; /*0x4A002E54*/
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u32 control_ddrio_2; /*0x4A002E58*/
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u32 control_hyst_1; /*0x4A002E5C*/
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u32 control_usbb_hsic_control; /*0x4A002E60*/
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u32 control_c2c; /*0x4A002E64*/
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u32 control_core_control_spare_rw; /*0x4A002E68*/
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u32 control_core_control_spare_r; /*0x4A002E6C*/
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u32 control_core_control_spare_r_c0; /*0x4A002E70*/
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u32 control_srcomp_north_side; /*0x4A002E74*/
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u32 control_srcomp_south_side; /*0x4A002E78*/
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u32 control_srcomp_east_side; /*0x4A002E7C*/
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u32 control_srcomp_west_side; /*0x4A002E80*/
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u32 control_srcomp_code_latch; /*0x4A002E84*/
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u32 pad3[3680198];
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u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
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u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
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u32 control_padconf_mode; /* 0x4AE0CDA8 */
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u32 control_xtal_oscillator; /* 0x4AE0CDAC */
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u32 control_i2c_2; /* 0x4AE0CDB0 */
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u32 control_ckobuffer; /* 0x4AE0CDB4 */
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u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
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u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
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u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
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u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
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u32 control_efuse_1; /* 0x4AE0CDC8 */
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u32 control_efuse_2; /* 0x4AE0CDCC */
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u32 control_efuse_3; /* 0x4AE0CDD0 */
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u32 control_efuse_4; /* 0x4AE0CDD4 */
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u32 control_efuse_5; /* 0x4AE0CDD8 */
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u32 control_efuse_6; /* 0x4AE0CDDC */
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u32 control_efuse_7; /* 0x4AE0CDE0 */
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u32 control_efuse_8; /* 0x4AE0CDE4 */
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u32 control_efuse_9; /* 0x4AE0CDE8 */
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u32 control_efuse_10; /* 0x4AE0CDEC */
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u32 control_efuse_11; /* 0x4AE0CDF0 */
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u32 control_efuse_12; /* 0x4AE0CDF4 */
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u32 control_efuse_13; /* 0x4AE0CDF8 */
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};
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/* Output impedance control */
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#define ds_120_ohm 0x0
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#define ds_60_ohm 0x1
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#define ds_45_ohm 0x2
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#define ds_30_ohm 0x3
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#define ds_mask 0x3
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/* Slew rate control */
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#define sc_slow 0x0
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#define sc_medium 0x1
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#define sc_fast 0x2
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#define sc_na 0x3
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#define sc_mask 0x3
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/* Target capacitance control */
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#define lb_5_12_pf 0x0
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#define lb_12_25_pf 0x1
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#define lb_25_50_pf 0x2
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#define lb_50_80_pf 0x3
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#define lb_mask 0x3
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#define usb_i_mask 0x7
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#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
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#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
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#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
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#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
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#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
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#define EFUSE_1 0x45145100
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#define EFUSE_2 0x45145100
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#define EFUSE_3 0x45145100
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#define EFUSE_4 0x45145100
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#endif /* __ASSEMBLY__ */
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/*
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* Non-secure SRAM Addresses
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* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
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* at 0x40304000(EMU base) so that our code works for both EMU and GP
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*/
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#define NON_SECURE_SRAM_START 0x40304000
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#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_ROM_VECT_BASE 0x4031F000
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/* Temporary SRAM stack used while low level init is done */
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#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
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#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
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/*
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* SRAM scratch space entries
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*/
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#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
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#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
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#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
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#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
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#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
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/* Silicon revisions */
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#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
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#define OMAP4430_ES1_0 0x44300100
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#define OMAP4430_ES2_0 0x44300200
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#define OMAP4430_ES2_1 0x44300210
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#define OMAP4430_ES2_2 0x44300220
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#define OMAP4430_ES2_3 0x44300230
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#define OMAP4460_ES1_0 0x44600100
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#define OMAP4460_ES1_1 0x44600110
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/* ROM code defines */
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/* Boot device */
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#define BOOT_DEVICE_MASK 0xFF
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#define BOOT_DEVICE_OFFSET 0x8
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#define DEV_DESC_PTR_OFFSET 0x4
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#define DEV_DATA_PTR_OFFSET 0x18
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#define BOOT_MODE_OFFSET 0x8
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#define RESET_REASON_OFFSET 0x9
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#define CH_FLAGS_OFFSET 0xA
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#define CH_FLAGS_CHSETTINGS (0x1 << 0)
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#define CH_FLAGS_CHRAM (0x1 << 1)
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#define CH_FLAGS_CHFLASH (0x1 << 2)
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#define CH_FLAGS_CHMMCSD (0x1 << 3)
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#ifndef __ASSEMBLY__
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struct omap_boot_parameters {
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char *boot_message;
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unsigned int mem_boot_descriptor;
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unsigned char omap_bootdevice;
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unsigned char reset_reason;
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unsigned char ch_flags;
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};
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#endif /* __ASSEMBLY__ */
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#endif
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