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086511fc96
The Xilinx ML507 Board is a Virtex 5 prototyping board that includes, among others: -Virtex 5 FX FPGA (With a ppc440x5 in it) -256MB of SDRAM2 -32MB of Flash -I2C Eeprom -System ACE chip -Serial ATA connectors -RS232 Level Conversors -Ethernet Transceiver This patch gives support to a standard design produced by EDK for this board: ppc440, uartlite, xilinx_int and flash - Includes Changes propossed by Stefan Roese and Michal Simek Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
35 lines
1.3 KiB
C
35 lines
1.3 KiB
C
/*
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* (C) Copyright 2008
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* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
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* This work has been supported by: QTechnology http://qtec.com/
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* based on xparameters-ml507.h by Xilinx
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef XPARAMETER_H
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#define XPARAMETER_H
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#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
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#define XPAR_INTC_0_BASEADDR 0x81800000
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#define XPAR_UARTLITE_0_BASEADDR 0x84000000
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#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
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#define XPAR_LLTEMAC_0_BASEADDR 0x81c00000
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#define XPAR_FLASH_MEM0_BASEADDR 0xFC000000
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#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
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#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
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#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
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#endif
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