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086511fc96
The Xilinx ML507 Board is a Virtex 5 prototyping board that includes, among others: -Virtex 5 FX FPGA (With a ppc440x5 in it) -256MB of SDRAM2 -32MB of Flash -I2C Eeprom -System ACE chip -Serial ATA connectors -RS232 Level Conversors -Ethernet Transceiver This patch gives support to a standard design produced by EDK for this board: ppc440, uartlite, xilinx_int and flash - Includes Changes propossed by Stefan Roese and Michal Simek Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/*
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* (C) Copyright 2008
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* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
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* This work has been supported by: QTechnology http://qtec.com/
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/processor.h>
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int board_pre_init(void)
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{
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return 0;
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}
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int checkboard(void)
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{
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puts ("ML507 Board\n");
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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return CFG_SDRAM_SIZE_MB * 1024 * 1024;
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}
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void get_sys_info(sys_info_t * sysInfo)
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{
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sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
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sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
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sysInfo->freqPCI = 0;
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return;
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}
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