mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
173 lines
4.9 KiB
INI
173 lines
4.9 KiB
INI
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2013 Seco USA Inc
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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#define __ASSEMBLY__
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#include <config.h>
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#include "asm/arch/mx6-ddr.h"
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#include "asm/arch/iomux.h"
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#include "asm/arch/crm_regs.h"
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/* DDR IO TYPE */
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
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/* DATA STROBE */
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
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/* DATA */
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
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/* ADDRESS */
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028
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DATA 4, MX6_IOM_DRAM_CAS, 0x00000028
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DATA 4, MX6_IOM_DRAM_RAS, 0x00000028
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/* CONTROL */
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
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DATA 4, MX6_IOM_DRAM_RESET, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028
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/* CLOCK */
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
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/*
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* DDR3 SETTINGS
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* Read Data Bit Delay
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*/
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
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/* Write Leveling */
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
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/* DQS gating, read delay, write delay calibration values */
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C
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/* Read calibration */
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45
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/* write calibration */
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C
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/* Complete calibration by forced measurement: */
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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/*
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* MMDC init:
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* in DDR3, 64-bit mode, only MMDC0 is init
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*/
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
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DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
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DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
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/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
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/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
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DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
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/* Initialize DDR3 on CS_0 and CS_1 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
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/* P0 01c */
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/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
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/*ZQ - Calibrationi */
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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/* set the default clock gate to save power */
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DATA 4, CCM_CCGR0, 0x00C03F3F
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DATA 4, CCM_CCGR1, 0x0030FC03
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DATA 4, CCM_CCGR2, 0x0FFFC000
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DATA 4, CCM_CCGR3, 0x3FF00000
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DATA 4, CCM_CCGR4, 0x00FFF300
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DATA 4, CCM_CCGR5, 0x0F0000C3
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DATA 4, CCM_CCGR6, 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
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DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
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