mirror of
https://github.com/brain-hackers/u-boot-brain
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e64987a892
This patch adds Lime GDC support together with support for the PWM backlight control through the w83782d chip. The reset pin of the latter is attached to GPIO, so we need to reset it in early_board_init_r. Signed-off-by: Anatolij Gustschin <agust@denx.de>
120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
/*
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* (C) Copyright 2008
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/*
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* TLB 1: 64M Non-cacheable, guarded
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* 0xfc000000 64M FLASH
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 2: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM First half
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*/
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SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 3: 256M Non-cacheable, guarded
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* 0x90000000 256M PCI1 MEM Second half
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*/
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SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_256M, 1),
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#if defined(CFG_FPGA_BASE)
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/*
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* TLB 4: 1M Non-cacheable, guarded
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* 0xc0000000 1M FPGA and NAND
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*/
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SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_1M, 1),
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#endif
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/*
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* TLB 5: 64M Non-cacheable, guarded
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* 0xc8000000 16M LIME GDC framebuffer
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* 0xc9fc0000 256K LIME GDC MMIO
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* (0xcbfc0000 256K LIME GDC MMIO)
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* MMIO is relocatable and could be at 0xcbfc0000
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*/
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SET_TLB_ENTRY(1, CFG_LIME_BASE, CFG_LIME_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 6: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe200_0000 16M PCI1 IO
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*/
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SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
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* 0x00000000 512M DDR System memory
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* Without SPD EEPROM configured DDR, this must be setup manually.
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* Make sure the TLB count at the top of this table is correct.
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* Likely it needs to be increased by two for these entries.
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*/
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SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_256M, 1),
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SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 8, BOOKE_PAGESZ_256M, 1),
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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