mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-06 03:20:41 +09:00
9f9f009373
This erratum only applies to general purpose DDR controllers in LS2. It shouldn't be applied to DP-DDR controller. Check DDRC versoin number before applying workaround. Signed-off-by: York Sun <yorksun@freescale.com> |
||
---|---|---|
.. | ||
fsl | ||
mvebu |