mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ea70da142c
ROM configures certain firewalls based on its usage, which includes the one in front of boot peripherals. In specific case of boot peripherals, ROM does not open up the full address space corresponding to the peripherals. Like in OSPI, ROM only configures the firewall region for 32 bit address space and mark 64bit address space flash regions as in-accessible. When security-cfg is initialized by sysfw, all the non-configured firewalls are kept in bypass state using a global setting. Since ROM configured firewalls for certain peripherals, these will not be touched. So when bootloader touches any of the address space that ROM marked as in-accessible, system raises a firewall exception causing boot hang. It would have been ideal if sysfw cleans up the ROM configured boot peripheral firewalls. Given the memory overhead to store this information provided by ROM and the boot time increase in re configuring the firewalls, it is concluded to clean this up in bootloaders. So disable all the firewalls that ROM doesn't open up the full address space. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
298 lines
8.1 KiB
C
298 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* J721E: SoC specific initialization
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*
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* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/armv7_mpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sysfw-loader.h>
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#include "common.h"
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#include <asm/arch/sys_proto.h>
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#include <linux/soc/ti/ti_sci_protocol.h>
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <dm/pinctrl.h>
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_K3_LOAD_SYSFW
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#ifdef CONFIG_TI_SECURE_DEVICE
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struct fwl_data cbass_hc_cfg0_fwls[] = {
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{ "PCIE0_CFG", 2560, 8 },
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{ "PCIE1_CFG", 2561, 8 },
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{ "USB3SS0_CORE", 2568, 4 },
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{ "USB3SS1_CORE", 2570, 4 },
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{ "EMMC8SS0_CFG", 2576, 4 },
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{ "UFS_HCI0_CFG", 2580, 4 },
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{ "SERDES0", 2584, 1 },
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{ "SERDES1", 2585, 1 },
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}, cbass_hc0_fwls[] = {
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{ "PCIE0_HP", 2528, 24 },
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{ "PCIE0_LP", 2529, 24 },
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{ "PCIE1_HP", 2530, 24 },
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{ "PCIE1_LP", 2531, 24 },
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}, cbass_rc_cfg0_fwls[] = {
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{ "EMMCSD4SS0_CFG", 2380, 4 },
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}, cbass_rc0_fwls[] = {
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{ "GPMC0", 2310, 8 },
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}, infra_cbass0_fwls[] = {
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{ "PLL_MMR0", 8, 26 },
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{ "CTRL_MMR0", 9, 16 },
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}, mcu_cbass0_fwls[] = {
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{ "MCU_R5FSS0_CORE0", 1024, 4 },
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{ "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
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{ "MCU_R5FSS0_CORE1", 1028, 4 },
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{ "MCU_FSS0_CFG", 1032, 12 },
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{ "MCU_FSS0_S1", 1033, 8 },
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{ "MCU_FSS0_S0", 1036, 8 },
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{ "MCU_PSROM49152X32", 1048, 1 },
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{ "MCU_MSRAM128KX64", 1050, 8 },
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{ "MCU_CTRL_MMR0", 1200, 8 },
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{ "MCU_PLL_MMR0", 1201, 3 },
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{ "MCU_CPSW0", 1220, 2 },
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}, wkup_cbass0_fwls[] = {
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{ "WKUP_CTRL_MMR0", 131, 16 },
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};
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#endif
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#endif
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static void mmr_unlock(u32 base, u32 partition)
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{
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/* Translate the base address */
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phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
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/* Unlock the requested partition if locked using two-step sequence */
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writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
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writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
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}
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static void ctrl_mmr_unlock(void)
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{
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/* Unlock all WKUP_CTRL_MMR0 module registers */
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
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/* Unlock all MCU_CTRL_MMR0 module registers */
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mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
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/* Unlock all CTRL_MMR0 module registers */
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mmr_unlock(CTRL_MMR0_BASE, 0);
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mmr_unlock(CTRL_MMR0_BASE, 1);
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mmr_unlock(CTRL_MMR0_BASE, 2);
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mmr_unlock(CTRL_MMR0_BASE, 3);
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mmr_unlock(CTRL_MMR0_BASE, 4);
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mmr_unlock(CTRL_MMR0_BASE, 5);
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mmr_unlock(CTRL_MMR0_BASE, 6);
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mmr_unlock(CTRL_MMR0_BASE, 7);
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}
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/*
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* This uninitialized global variable would normal end up in the .bss section,
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* but the .bss is cleared between writing and reading this variable, so move
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* it to the .data section.
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*/
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u32 bootindex __attribute__((section(".data")));
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static void store_boot_index_from_rom(void)
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{
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bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
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}
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void board_init_f(ulong dummy)
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{
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#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
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struct udevice *dev;
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int ret;
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#endif
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/*
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* Cannot delay this further as there is a chance that
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* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
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*/
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store_boot_index_from_rom();
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/* Make all control module registers accessible */
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ctrl_mmr_unlock();
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#ifdef CONFIG_CPU_V7R
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disable_linefill_optimization();
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setup_k3_mpu_regions();
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#endif
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/* Init DM early */
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spl_early_init();
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#ifdef CONFIG_K3_LOAD_SYSFW
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/*
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* Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
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* regardless of the result of pinctrl. Do this without probing the
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* device, but instead by searching the device that would request the
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* given sequence number if probed. The UART will be used by the system
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* firmware (SYSFW) image for various purposes and SYSFW depends on us
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* to initialize its pin settings.
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*/
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ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
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if (!ret)
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pinctrl_select_state(dev, "default");
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/*
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* Load, start up, and configure system controller firmware. Provide
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* the U-Boot console init function to the SYSFW post-PM configuration
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* callback hook, effectively switching on (or over) the console
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* output.
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*/
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k3_sysfw_loader(preloader_console_init);
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/* Disable ROM configured firewalls right after loading sysfw */
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#ifdef CONFIG_TI_SECURE_DEVICE
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remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
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remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
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remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
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remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
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remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
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remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
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remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
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#endif
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#else
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/* Prepare console output */
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preloader_console_init();
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#endif
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/* Perform EEPROM-based board detection */
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do_board_detect();
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#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
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ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
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&dev);
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if (ret)
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printf("AVS init failed: %d\n", ret);
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#endif
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#if defined(CONFIG_K3_J721E_DDRSS)
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret)
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panic("DRAM init failed: %d\n", ret);
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#endif
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}
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u32 spl_boot_mode(const u32 boot_device)
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{
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switch (boot_device) {
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case BOOT_DEVICE_MMC1:
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return MMCSD_MODE_EMMCBOOT;
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case BOOT_DEVICE_MMC2:
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return MMCSD_MODE_FS;
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default:
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return MMCSD_MODE_RAW;
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}
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}
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static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
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{
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u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
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WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
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bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
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BOOT_MODE_B_SHIFT;
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if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
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bootmode = BOOT_DEVICE_SPI;
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if (bootmode == BOOT_DEVICE_MMC2) {
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u32 port = (main_devstat &
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MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
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MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
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if (port == 0x0)
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bootmode = BOOT_DEVICE_MMC1;
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}
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return bootmode;
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}
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u32 spl_boot_device(void)
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{
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u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
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u32 main_devstat;
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if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
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printf("ERROR: MCU only boot is not yet supported\n");
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return BOOT_DEVICE_RAM;
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}
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/* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
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main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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/* ToDo: Add support for backup boot media */
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return __get_primary_bootmedia(main_devstat, wkup_devstat);
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}
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#endif
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#ifdef CONFIG_SYS_K3_SPL_ATF
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#define J721E_DEV_MCU_RTI0 262
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#define J721E_DEV_MCU_RTI1 263
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#define J721E_DEV_MCU_ARMSS0_CPU0 250
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#define J721E_DEV_MCU_ARMSS0_CPU1 251
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void release_resources_for_core_shutdown(void)
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{
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struct ti_sci_handle *ti_sci;
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struct ti_sci_dev_ops *dev_ops;
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struct ti_sci_proc_ops *proc_ops;
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int ret;
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u32 i;
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const u32 put_device_ids[] = {
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J721E_DEV_MCU_RTI0,
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J721E_DEV_MCU_RTI1,
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};
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ti_sci = get_ti_sci_handle();
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dev_ops = &ti_sci->ops.dev_ops;
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proc_ops = &ti_sci->ops.proc_ops;
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/* Iterate through list of devices to put (shutdown) */
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for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
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u32 id = put_device_ids[i];
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ret = dev_ops->put_device(ti_sci, id);
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if (ret)
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panic("Failed to put device %u (%d)\n", id, ret);
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}
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const u32 put_core_ids[] = {
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J721E_DEV_MCU_ARMSS0_CPU1,
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J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
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};
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/* Iterate through list of cores to put (shutdown) */
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for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
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u32 id = put_core_ids[i];
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/*
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* Queue up the core shutdown request. Note that this call
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* needs to be followed up by an actual invocation of an WFE
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* or WFI CPU instruction.
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*/
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ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
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if (ret)
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panic("Failed sending core %u shutdown message (%d)\n",
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id, ret);
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}
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}
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#endif
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