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69a3b81141
For K2E and K2L SoCs clock output from PASS PLL has to be enabled after NETCP domain and PA module are enabled. So create new function for that and call it after PA module is enabled. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
/*
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* keystone2: common clock header file
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_H
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#define __ASM_ARCH_CLOCK_H
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_SOC_K2HK
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#include <asm/arch/clock-k2hk.h>
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#endif
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#ifdef CONFIG_SOC_K2E
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#include <asm/arch/clock-k2e.h>
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#endif
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#ifdef CONFIG_SOC_K2L
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#include <asm/arch/clock-k2l.h>
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#endif
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#define MAIN_PLL CORE_PLL
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#include <asm/types.h>
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#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
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#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
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#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)
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enum clk_e {
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CLK_LIST(GENERATE_ENUM)
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};
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struct keystone_pll_regs {
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u32 reg0;
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u32 reg1;
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};
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/* PLL configuration data */
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struct pll_init_data {
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int pll;
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int pll_m; /* PLL Multiplier */
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int pll_d; /* PLL divider */
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int pll_od; /* PLL output divider */
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};
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extern const struct keystone_pll_regs keystone_pll_regs[];
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extern int dev_speeds[];
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extern int arm_speeds[];
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void init_plls(int num_pll, struct pll_init_data *config);
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void init_pll(const struct pll_init_data *data);
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unsigned long clk_get_rate(unsigned int clk);
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unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
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int clk_set_rate(unsigned int clk, unsigned long hz);
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void pass_pll_pa_clk_enable(void);
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int get_max_dev_speed(void);
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int get_max_arm_speed(void);
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#endif
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#endif
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