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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-31 06:18:51 +09:00
![Alexey Brodkin](/assets/img/avatar_default.png)
First of all U-Boot is not that performance oriented as real run-time software like OS or user bare-metal app so we may afford being not super fast as we only being executed once. That in return allows us to be more universal and support wider variety of devices. And looking forward that will significantly reduce maintenance and simplify support of newer architectures. And while at it we add quad-word accessors like readq(), writeq() etc. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
229 lines
7.1 KiB
C
229 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2014, 2020 Synopsys, Inc. All rights reserved.
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*/
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#ifndef __ASM_ARC_IO_H
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#define __ASM_ARC_IO_H
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#ifdef __ARCHS__
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/*
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* ARCv2 based HS38 cores are in-order issue, but still weakly ordered
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* due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
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*
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* Explicit barrier provided by DMB instruction
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* - Operand supports fine grained load/store/load+store semantics
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* - Ensures that selected memory operation issued before it will complete
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* before any subsequent memory operation of same type
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* - DMB guarantees SMP as well as local barrier semantics
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* (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
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* UP: barrier(), SMP: smp_*mb == *mb)
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* - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
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* in the general case. Plus it only provides full barrier.
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*/
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#define mb() asm volatile("dmb 3\n" : : : "memory")
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#define rmb() asm volatile("dmb 1\n" : : : "memory")
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#define wmb() asm volatile("dmb 2\n" : : : "memory")
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#else
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/*
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* ARCompact based cores (ARC700) only have SYNC instruction which is super
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* heavy weight as it flushes the pipeline as well.
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* There are no real SMP implementations of such cores.
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*/
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#define mb() asm volatile("sync\n" : : : "memory")
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#endif
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#ifdef __ARCHS__
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#else
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#define __iormb() asm volatile("" : : : "memory")
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#define __iowmb() asm volatile("" : : : "memory")
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#endif
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static inline void sync(void)
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{
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/* Not yet implemented */
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}
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#define __arch_getb(a) (*(unsigned char *)(a))
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#define __arch_getw(a) (*(unsigned short *)(a))
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#define __arch_getl(a) (*(unsigned int *)(a))
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#define __arch_getq(a) (*(unsigned long long *)(a))
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#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
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#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
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#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
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#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
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#define __raw_writeb(v, a) __arch_putb(v, a)
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#define __raw_writew(v, a) __arch_putw(v, a)
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#define __raw_writel(v, a) __arch_putl(v, a)
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#define __raw_writeq(v, a) __arch_putq(v, a)
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#define __raw_readb(a) __arch_getb(a)
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#define __raw_readw(a) __arch_getw(a)
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#define __raw_readl(a) __arch_getl(a)
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#define __raw_readq(a) __arch_getq(a)
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static inline void __raw_writesb(unsigned long addr, const void *data,
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int bytelen)
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{
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u8 *buf = (uint8_t *)data;
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while (bytelen--)
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__arch_putb(*buf++, addr);
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}
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static inline void __raw_writesw(unsigned long addr, const void *data,
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int wordlen)
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{
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u16 *buf = (uint16_t *)data;
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while (wordlen--)
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__arch_putw(*buf++, addr);
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}
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static inline void __raw_writesl(unsigned long addr, const void *data,
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int longlen)
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{
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u32 *buf = (uint32_t *)data;
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while (longlen--)
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__arch_putl(*buf++, addr);
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}
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static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
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{
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u8 *buf = (uint8_t *)data;
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while (bytelen--)
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*buf++ = __arch_getb(addr);
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}
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static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
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{
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u16 *buf = (uint16_t *)data;
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while (wordlen--)
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*buf++ = __arch_getw(addr);
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}
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static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
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{
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u32 *buf = (uint32_t *)data;
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while (longlen--)
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*buf++ = __arch_getl(addr);
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}
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses.
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*/
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#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
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__raw_readq(c)); __r; })
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#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
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#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
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cpu_to_le16(v), (c)))
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#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \
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cpu_to_le32(v), (c)))
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#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \
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cpu_to_le64(v), (c)))
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/*
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* MMIO can also get buffered/optimized in micro-arch, so barriers needed
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* Based on ARM model for the typical use case
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*
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* <ST [DMA buffer]>
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* <writel MMIO "go" reg>
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* or:
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* <readl MMIO "status" reg>
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* <LD [DMA buffer]>
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*
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* http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
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#define writeb(v, c) ({ __iowmb(); writeb_relaxed(v, c); })
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#define writew(v, c) ({ __iowmb(); writew_relaxed(v, c); })
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#define writel(v, c) ({ __iowmb(); writel_relaxed(v, c); })
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#define writeq(v, c) ({ __iowmb(); writeq_relaxed(v, c); })
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#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
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#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
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#define out_le32(a, v) out_arch(l, le32, a, v)
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#define out_le16(a, v) out_arch(w, le16, a, v)
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#define in_le32(a) in_arch(l, le32, a)
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#define in_le16(a) in_arch(w, le16, a)
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#define out_be32(a, v) out_arch(l, be32, a, v)
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#define out_be16(a, v) out_arch(w, be16, a, v)
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#define in_be32(a) in_arch(l, be32, a)
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#define in_be16(a) in_arch(w, be16, a)
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#define out_8(a, v) __raw_writeb(v, a)
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#define in_8(a) __raw_readb(a)
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/*
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* Clear and set bits in one shot. These macros can be used to clear and
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* set multiple bits in a register using a single call. These macros can
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* also be used to set a multiple-bit bit pattern using a mask, by
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* specifying the mask in the 'clear' parameter and the new bit pattern
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* in the 'set' parameter.
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*/
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#define clrbits(type, addr, clear) \
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out_##type((addr), in_##type(addr) & ~(clear))
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#define setbits(type, addr, set) \
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out_##type((addr), in_##type(addr) | (set))
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#define clrsetbits(type, addr, clear, set) \
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out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
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#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
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#define setbits_be32(addr, set) setbits(be32, addr, set)
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#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
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#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
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#define setbits_le32(addr, set) setbits(le32, addr, set)
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#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
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#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
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#define setbits_be16(addr, set) setbits(be16, addr, set)
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#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
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#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
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#define setbits_le16(addr, set) setbits(le16, addr, set)
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#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
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#define clrbits_8(addr, clear) clrbits(8, addr, clear)
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#define setbits_8(addr, set) setbits(8, addr, set)
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#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
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#include <asm-generic/io.h>
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#endif /* __ASM_ARC_IO_H */
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