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1960b01034
- hclk/pclk_div range should use '<=' instead of '<' - use GPLL for pd_bus clock source - pd_bus HCLK/PCLK clock rate should not bigger than ACLK Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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.. | ||
clk_rk3036.c | ||
clk_rk3188.c | ||
clk_rk3288.c | ||
clk_rk3328.c | ||
clk_rk3368.c | ||
clk_rk3399.c | ||
Makefile |