Vikas Manocha 280057bd7d stm32f7: use stm32f7 gpio driver supporting driver model ... With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>		2017-05-08 11:57:21 -04:00
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aspeed	aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation	2017-02-08 15:56:30 -05:00
at91	dm: allow limiting pre-reloc markings to spl or tpl	2017-03-16 16:03:44 -06:00
exynos	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
rockchip	rockchip: clk: rk3399: 24MHz is not a power of 2	2017-04-04 20:01:57 -06:00
tegra	clock: implement a driver for the Tegra CAR	2016-09-27 09:11:02 -07:00
uniphier	clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clock	2017-01-29 20:59:08 +09:00
clk_boston.c	clk: boston: Providea simple driver for Boston board clocks	2016-09-21 15:04:32 +02:00
clk_fixed_rate.c	dm: core: Replace of_offset with accessor	2017-02-08 06:12:14 -07:00
clk_pic32.c	dm: core: Replace of_offset with accessor	2017-02-08 06:12:14 -07:00
clk_sandbox_test.c	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
clk_sandbox.c	clk: sandbox: don't check clk ID against 0	2016-06-24 17:24:35 -04:00
clk_stm32f7.c	stm32f7: use stm32f7 gpio driver supporting driver model	2017-05-08 11:57:21 -04:00
clk_zynq.c	clk: zynq: Add optional ethernet emio clock source support	2017-02-17 10:22:46 +01:00
clk_zynqmp.c	clk: zynqmp: Add clock driver support for zynqmp	2017-01-10 10:18:12 +01:00
clk-uclass.c	dm: core: Replace of_offset with accessor	2017-02-08 06:12:14 -07:00
Kconfig	clk: zynq: Add zynq clock framework driver	2017-02-17 10:22:46 +01:00
Makefile	clk: stm32f7: add clock driver for stm32f7 family	2017-03-17 14:15:12 -04:00