mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-13 00:03:26 +09:00
![Masahiro Yamada](/assets/img/avatar_default.png)
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
589 lines
14 KiB
C
589 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Timesys Corporation
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* Copyright 2015 General Electric Company
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* Copyright 2012 Freescale Semiconductor, Inc.
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*/
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#include <image.h>
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <env.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/libfdt.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <power/regulator.h>
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#include <power/da9063_pmic.h>
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#include <input.h>
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#include <pwm.h>
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#include <version.h>
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#include <stdlib.h>
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#include <dm/root.h>
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#include "../common/ge_common.h"
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#include "../common/vpd_reader.h"
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#include "../../../drivers/net/e1000.h"
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#include <pci.h>
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#include <panel.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int confidx; /* Default to generic. */
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static struct vpd_cache vpd;
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#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static int mx6_rgmii_rework(struct phy_device *phydev)
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{
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/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
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/* set device address 0x7 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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/* offset 0x8016: CLK_25M Clock Select */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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/* enable register write, no post increment, address 0x7 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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/* set to 125 MHz from local PLL source */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
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/* rgmii tx clock delay enable */
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/* set debug port address: SerDes Test and System Mode Control */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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/* enable rgmii tx clock delay */
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/* set the reserved bits to avoid board specific voltage peak issue*/
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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mx6_rgmii_rework(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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static void do_enable_backlight(struct display_info_t const *dev)
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{
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struct udevice *panel;
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int ret;
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ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
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if (ret) {
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printf("Could not find panel: %d\n", ret);
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return;
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}
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panel_set_backlight(panel, 100);
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panel_enable_backlight(panel);
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}
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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static int is_b850v3(void)
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{
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return confidx == 3;
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}
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static int detect_lcd(struct display_info_t const *dev)
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{
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return !is_b850v3();
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = -1,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_lcd,
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.enable = do_enable_backlight,
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.mode = {
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.name = "G121X1-L03",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 20,
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.right_margin = 300,
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.upper_margin = 30,
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.lower_margin = 8,
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.hsync_len = 1,
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.vsync_len = 1,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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.bus = -1,
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.addr = 3,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void enable_videopll(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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s32 timeout = 100000;
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setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
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/* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
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* |
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* PLL5
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* |
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* CS2CDR[LDB_DI0_CLK_SEL]
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* |
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* +----> LDB_DI0_SERIAL_CLK_ROOT
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* |
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* +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
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*/
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clrsetbits_le32(&ccm->analog_pll_video,
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BM_ANADIG_PLL_VIDEO_DIV_SELECT |
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BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
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BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
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BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
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writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
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writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
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clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
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while (timeout--)
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if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
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break;
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if (timeout < 0)
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printf("Warning: video pll lock timeout!\n");
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clrsetbits_le32(&ccm->analog_pll_video,
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BM_ANADIG_PLL_VIDEO_BYPASS,
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BM_ANADIG_PLL_VIDEO_ENABLE);
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}
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static void setup_display_b850v3(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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enable_videopll();
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/* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
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setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
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imx_setup_hdmi();
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/* Set LDB_DI0 as clock source for IPU_DI0 */
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clrsetbits_le32(&mxc_ccm->chsccdr,
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
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(CHSCCDR_CLK_SEL_LDB_DI0 <<
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
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/* Turn on IPU LDB DI0 clocks */
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setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
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enable_ipu_clock();
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writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
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IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
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IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
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IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
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IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
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IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
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IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
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IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
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&iomux->gpr[2]);
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clrbits_le32(&iomux->gpr[3],
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IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
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IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
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IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
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}
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static void setup_display_bx50v3(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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enable_videopll();
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/* When a reset/reboot is performed the display power needs to be turned
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* off for atleast 500ms. The boot time is ~300ms, we need to wait for
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* an additional 200ms here. Unfortunately we use external PMIC for
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* doing the reset, so can not differentiate between POR vs soft reset
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*/
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mdelay(200);
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/* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
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setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
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/* Set LDB_DI0 as clock source for IPU_DI0 */
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clrsetbits_le32(&mxc_ccm->chsccdr,
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
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(CHSCCDR_CLK_SEL_LDB_DI0 <<
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
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/* Turn on IPU LDB DI0 clocks */
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setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
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enable_ipu_clock();
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writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
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IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
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IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
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IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
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&iomux->gpr[2]);
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clrsetbits_le32(&iomux->gpr[3],
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IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
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(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
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IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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#define VPD_TYPE_INVALID 0x00
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#define VPD_BLOCK_NETWORK 0x20
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#define VPD_BLOCK_HWID 0x44
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#define VPD_PRODUCT_B850 1
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#define VPD_PRODUCT_B650 2
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#define VPD_PRODUCT_B450 3
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#define VPD_HAS_MAC1 0x1
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#define VPD_HAS_MAC2 0x2
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#define VPD_MAC_ADDRESS_LENGTH 6
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struct vpd_cache {
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bool is_read;
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u8 product_id;
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u8 has;
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unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
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unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
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};
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/*
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* Extracts MAC and product information from the VPD.
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*/
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static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
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size_t size, u8 const *data)
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{
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if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
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size >= 1) {
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vpd->product_id = data[0];
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} else if (id == VPD_BLOCK_NETWORK && version == 1 &&
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type != VPD_TYPE_INVALID) {
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if (size >= 6) {
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vpd->has |= VPD_HAS_MAC1;
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memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
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}
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if (size >= 12) {
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vpd->has |= VPD_HAS_MAC2;
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memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
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}
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}
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return 0;
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}
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static void process_vpd(struct vpd_cache *vpd)
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{
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int fec_index = 0;
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int i210_index = -1;
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if (!vpd->is_read) {
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printf("VPD wasn't read");
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return;
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}
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if (vpd->has & VPD_HAS_MAC1)
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eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
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env_set("ethact", "eth0");
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switch (vpd->product_id) {
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case VPD_PRODUCT_B450:
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env_set("confidx", "1");
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i210_index = 1;
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break;
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case VPD_PRODUCT_B650:
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env_set("confidx", "2");
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i210_index = 1;
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break;
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case VPD_PRODUCT_B850:
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env_set("confidx", "3");
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i210_index = 2;
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break;
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}
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if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
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eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
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}
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static iomux_v3_cfg_t const misc_pads[] = {
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MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
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MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
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MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
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MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
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MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
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MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
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MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
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};
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#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
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#define WIFI_EN IMX_GPIO_NR(6, 14)
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int board_early_init_f(void)
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{
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imx_iomux_v3_setup_multiple_pads(misc_pads,
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ARRAY_SIZE(misc_pads));
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#if defined(CONFIG_VIDEO_IPUV3)
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/* Set LDB clock to Video PLL */
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select_ldb_di_clock_source(MXC_PLL5_CLK);
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#endif
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return 0;
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}
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static void set_confidx(const struct vpd_cache* vpd)
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{
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switch (vpd->product_id) {
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case VPD_PRODUCT_B450:
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confidx = 1;
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break;
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case VPD_PRODUCT_B650:
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confidx = 2;
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break;
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case VPD_PRODUCT_B850:
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confidx = 3;
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break;
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}
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}
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int board_init(void)
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{
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if (!read_vpd(&vpd, vpd_callback)) {
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int ret, rescan;
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vpd.is_read = true;
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set_confidx(&vpd);
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ret = fdtdec_resetup(&rescan);
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if (!ret && rescan) {
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dm_uninit();
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dm_init_and_scan(false);
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}
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}
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|
|
gpio_request(SUS_S3_OUT, "sus_s3_out");
|
|
gpio_direction_output(SUS_S3_OUT, 1);
|
|
|
|
gpio_request(WIFI_EN, "wifi_en");
|
|
gpio_direction_output(WIFI_EN, 1);
|
|
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
|
if (is_b850v3())
|
|
setup_display_b850v3();
|
|
else
|
|
setup_display_bx50v3();
|
|
#endif
|
|
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
static const struct boot_mode board_boot_modes[] = {
|
|
/* 4 bit bus width */
|
|
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
|
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
|
{NULL, 0},
|
|
};
|
|
#endif
|
|
|
|
void pmic_init(void)
|
|
{
|
|
struct udevice *reg;
|
|
int ret, i;
|
|
static const char * const bucks[] = {
|
|
"bcore1",
|
|
"bcore2",
|
|
"bpro",
|
|
"bmem",
|
|
"bio",
|
|
"bperi",
|
|
};
|
|
|
|
for (i = 0; i < ARRAY_SIZE(bucks); i++) {
|
|
ret = regulator_get_by_devname(bucks[i], ®);
|
|
if (reg < 0) {
|
|
printf("%s(): Unable to get regulator %s: %d\n",
|
|
__func__, bucks[i], ret);
|
|
continue;
|
|
}
|
|
regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
|
|
}
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
process_vpd(&vpd);
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
|
|
if (is_b850v3())
|
|
env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
|
|
else
|
|
env_set("videoargs", "video=LVDS-1:1024x768@65");
|
|
|
|
/* board specific pmic init */
|
|
pmic_init();
|
|
|
|
check_time();
|
|
|
|
pci_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Removes the 'eth[0-9]*addr' environment variable with the given index
|
|
*
|
|
* @param index [in] the index of the eth_device whose variable is to be removed
|
|
*/
|
|
static void remove_ethaddr_env_var(int index)
|
|
{
|
|
char env_var_name[9];
|
|
|
|
sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
|
|
env_set(env_var_name, NULL);
|
|
}
|
|
|
|
int last_stage_init(void)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* Remove first three ethaddr which may have been created by
|
|
* function process_vpd().
|
|
*/
|
|
for (i = 0; i < 3; ++i)
|
|
remove_ethaddr_env_var(i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
printf("BOARD: %s\n", CONFIG_BOARD_NAME);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
{
|
|
char *rtc_status = env_get("rtc_status");
|
|
|
|
fdt_setprop(blob, 0, "ge,boot-ver", version_string,
|
|
strlen(version_string) + 1);
|
|
|
|
fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
|
|
strlen(rtc_status) + 1);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
if (!vpd.is_read)
|
|
return strcmp(name, "imx6q-bx50v3");
|
|
|
|
switch (vpd.product_id) {
|
|
case VPD_PRODUCT_B450:
|
|
return strcmp(name, "imx6q-b450v3");
|
|
case VPD_PRODUCT_B650:
|
|
return strcmp(name, "imx6q-b650v3");
|
|
case VPD_PRODUCT_B850:
|
|
return strcmp(name, "imx6q-b850v3");
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
int embedded_dtb_select(void)
|
|
{
|
|
vpd.is_read = false;
|
|
return fdtdec_setup();
|
|
}
|