mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-19 03:03:22 +09:00
40f8dec54d
Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "mp.h"
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#ifdef CONFIG_MP
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void ft_fixup_cpu(void *blob)
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{
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int off;
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__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
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fdt32_t *reg;
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int addr_cells;
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u64 val;
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size_t *boot_code_size = &(__secondary_boot_code_size);
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off = fdt_path_offset(blob, "/cpus");
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if (off < 0) {
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puts("couldn't find /cpus node\n");
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return;
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}
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of_bus_default_count_cells(blob, off, &addr_cells, NULL);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
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if (reg) {
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val = spin_tbl_addr;
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val += id_to_core(of_read_number(reg, addr_cells))
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* SPIN_TABLE_ELEM_SIZE;
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val = cpu_to_fdt64(val);
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fdt_setprop_string(blob, off, "enable-method",
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"spin-table");
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fdt_setprop(blob, off, "cpu-release-addr",
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&val, sizeof(val));
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} else {
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puts("Warning: found cpu node without reg property\n");
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}
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off = fdt_node_offset_by_prop_value(blob, off, "device_type",
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"cpu", 4);
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}
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fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
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*boot_code_size);
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}
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#endif
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_MP
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ft_fixup_cpu(blob);
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#endif
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}
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