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https://github.com/brain-hackers/u-boot-brain
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fffad9264a
Add FSP related configuration for Braswell. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
90 lines
2.2 KiB
C
90 lines
2.2 KiB
C
/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSP_CONFIGS_H__
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#define __FSP_CONFIGS_H__
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#ifndef __ASSEMBLY__
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struct fsp_config_data {
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struct fsp_cfg_common common;
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struct upd_region fsp_upd;
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};
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struct fspinit_rtbuf {
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struct common_buf common; /* FSP common runtime data structure */
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};
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#endif
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/* FSP user configuration settings */
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#define MRC_INIT_TSEG_SIZE_1MB 1
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#define MRC_INIT_TSEG_SIZE_2MB 2
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#define MRC_INIT_TSEG_SIZE_4MB 4
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#define MRC_INIT_TSEG_SIZE_8MB 8
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#define MRC_INIT_MMIO_SIZE_1024MB 0x400
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#define MRC_INIT_MMIO_SIZE_1536MB 0x600
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#define MRC_INIT_MMIO_SIZE_2048MB 0x800
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#define IGD_DVMT50_PRE_ALLOC_32MB 0x01
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#define IGD_DVMT50_PRE_ALLOC_64MB 0x02
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#define IGD_DVMT50_PRE_ALLOC_96MB 0x03
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#define IGD_DVMT50_PRE_ALLOC_128MB 0x04
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#define IGD_DVMT50_PRE_ALLOC_160MB 0x05
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#define IGD_DVMT50_PRE_ALLOC_192MB 0x06
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#define IGD_DVMT50_PRE_ALLOC_224MB 0x07
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#define IGD_DVMT50_PRE_ALLOC_256MB 0x08
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#define IGD_DVMT50_PRE_ALLOC_288MB 0x09
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#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
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#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
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#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
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#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
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#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
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#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
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#define IGD_DVMT50_PRE_ALLOC_512MB 0x10
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#define APERTURE_SIZE_128MB 1
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#define APERTURE_SIZE_256MB 2
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#define APERTURE_SIZE_512MB 3
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#define GTT_SIZE_1MB 1
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#define GTT_SIZE_2MB 2
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#define DRAM_TYPE_DDR3 0
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#define DRAM_TYPE_LPDDR3 1
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#define SDCARD_MODE_DISABLED 0
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#define SDCARD_MODE_PCI 1
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#define SDCARD_MODE_ACPI 2
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#define LPE_MODE_DISABLED 0
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#define LPE_MODE_PCI 1
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#define LPE_MODE_ACPI 2
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#define CHV_SVID_CONFIG_0 0
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#define CHV_SVID_CONFIG_1 1
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#define CHV_SVID_CONFIG_2 2
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#define CHV_SVID_CONFIG_3 3
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#define EMMC_MODE_DISABLED 0
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#define EMMC_MODE_PCI 1
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#define EMMC_MODE_ACPI 2
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#define SATA_SPEED_GEN1 1
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#define SATA_SPEED_GEN2 2
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#define SATA_SPEED_GEN3 3
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#define ISP_PCI_DEV_CONFIG_1 1
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#define ISP_PCI_DEV_CONFIG_2 2
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#define ISP_PCI_DEV_CONFIG_3 3
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#define PNP_SETTING_DISABLED 0
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#define PNP_SETTING_POWER 1
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#define PNP_SETTING_PERF 2
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#define PNP_SETTING_POWER_AND_PERF 3
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#endif /* __FSP_CONFIGS_H__ */
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