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![Chin Liang See](/assets/img/avatar_default.png)
Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
362 lines
11 KiB
C
362 lines
11 KiB
C
/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock_manager.h>
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static const struct socfpga_clock_manager *clock_manager_base =
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(void *)SOCFPGA_CLKMGR_ADDRESS;
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#define CLKMGR_BYPASS_ENABLE 1
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#define CLKMGR_BYPASS_DISABLE 0
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#define CLKMGR_STAT_IDLE 0
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#define CLKMGR_STAT_BUSY 1
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#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
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#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
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#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
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#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
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#define CLEAR_BGP_EN_PWRDN \
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(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
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CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
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CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
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#define VCO_EN_BASE \
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(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
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CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
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CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
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static inline void cm_wait_for_lock(uint32_t mask)
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{
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register uint32_t inter_val;
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do {
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inter_val = readl(&clock_manager_base->inter) & mask;
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} while (inter_val != mask);
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}
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/* function to poll in the fsm busy bit */
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static inline void cm_wait_for_fsm(void)
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{
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while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
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;
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}
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static inline void cm_write_bypass(uint32_t val)
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{
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writel(val, &clock_manager_base->bypass);
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cm_wait_for_fsm();
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static inline void cm_write_ctrl(uint32_t val)
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{
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writel(val, &clock_manager_base->ctrl);
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cm_wait_for_fsm();
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}
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/* function to write a clock register that has phase information */
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static inline void cm_write_with_phase(uint32_t value,
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uint32_t reg_address, uint32_t mask)
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{
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/* poll until phase is zero */
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while (readl(reg_address) & mask)
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;
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writel(value, reg_address);
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while (readl(reg_address) & mask)
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;
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}
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/*
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* Setup clocks while making no assumptions about previous state of the clocks.
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*
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* Start by being paranoid and gate all sw managed clocks
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* Put all plls in bypass
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* Put all plls VCO registers back to reset value (bandgap power down).
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* Put peripheral and main pll src to reset value to avoid glitch.
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* Delay 5 us.
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* Deassert bandgap power down and set numerator and denominator
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* Start 7 us timer.
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* set internal dividers
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* Wait for 7 us timer.
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* Enable plls
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* Set external dividers while plls are locking
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* Wait for pll lock
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* Assert/deassert outreset all.
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* Take all pll's out of bypass
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* Clear safe mode
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* set source main and peripheral clocks
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* Ungate clocks
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*/
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void cm_basic_init(const cm_config_t *cfg)
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{
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uint32_t start, timeout;
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/* Start by being paranoid and gate all sw managed clocks */
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/*
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* We need to disable nandclk
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* and then do another apb access before disabling
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* gatting off the rest of the periperal clocks.
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*/
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writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
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readl(&clock_manager_base->per_pll_en),
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&clock_manager_base->per_pll_en);
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/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
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writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
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CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
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&clock_manager_base->main_pll_en);
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writel(0, &clock_manager_base->sdr_pll_en);
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/* now we can gate off the rest of the peripheral clocks */
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writel(0, &clock_manager_base->per_pll_en);
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/* Put all plls in bypass */
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cm_write_bypass(
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CLKMGR_BYPASS_PERPLLSRC_SET(
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CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
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CLKMGR_BYPASS_SDRPLLSRC_SET(
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CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
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CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
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CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
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CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
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/*
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* Put all plls VCO registers back to reset value.
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* Some code might have messed with them.
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*/
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writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
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&clock_manager_base->main_pll_vco);
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writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
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&clock_manager_base->per_pll_vco);
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writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
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&clock_manager_base->sdr_pll_vco);
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/*
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* The clocks to the flash devices and the L4_MAIN clocks can
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* glitch when coming out of safe mode if their source values
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* are different from their reset value. So the trick it to
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* put them back to their reset state, and change input
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* after exiting safe mode but before ungating the clocks.
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*/
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writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
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&clock_manager_base->per_pll_src);
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writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
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&clock_manager_base->main_pll_l4src);
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/* read back for the required 5 us delay. */
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readl(&clock_manager_base->main_pll_vco);
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readl(&clock_manager_base->per_pll_vco);
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readl(&clock_manager_base->sdr_pll_vco);
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/*
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* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
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* with numerator and denominator.
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*/
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writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
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CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->main_pll_vco);
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writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
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CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->per_pll_vco);
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writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
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cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
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CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->sdr_pll_vco);
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/*
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* Time starts here
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* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
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*/
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reset_timer();
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start = get_timer(0);
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/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
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timeout = 7;
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/* main mpu */
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writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
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/* main main clock */
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writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
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/* main for dbg */
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writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
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/* main for cfgs2fuser0clk */
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writel(cfg->cfg2fuser0clk,
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&clock_manager_base->main_pll_cfgs2fuser0clk);
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/* Peri emac0 50 MHz default to RMII */
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writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
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/* Peri emac1 50 MHz default to RMII */
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writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
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/* Peri QSPI */
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writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
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writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
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/* Peri pernandsdmmcclk */
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writel(cfg->pernandsdmmcclk,
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&clock_manager_base->per_pll_pernandsdmmcclk);
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/* Peri perbaseclk */
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writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
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/* Peri s2fuser1clk */
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writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
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/* 7 us must have elapsed before we can enable the VCO */
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while (get_timer(start) < timeout)
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;
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/* Enable vco */
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/* main pll vco */
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writel(cfg->main_vco_base | VCO_EN_BASE,
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&clock_manager_base->main_pll_vco);
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/* periferal pll */
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writel(cfg->peri_vco_base | VCO_EN_BASE,
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&clock_manager_base->per_pll_vco);
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/* sdram pll vco */
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writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
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cfg->sdram_vco_base | VCO_EN_BASE,
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&clock_manager_base->sdr_pll_vco);
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/* L3 MP and L3 SP */
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writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
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writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
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writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
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/* L4 MP, L4 SP, can0, and can1 */
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writel(cfg->perdiv, &clock_manager_base->per_pll_div);
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writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
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#define LOCKED_MASK \
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(CLKMGR_INTER_SDRPLLLOCKED_MASK | \
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CLKMGR_INTER_PERPLLLOCKED_MASK | \
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CLKMGR_INTER_MAINPLLLOCKED_MASK)
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cm_wait_for_lock(LOCKED_MASK);
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/* write the sdram clock counters before toggling outreset all */
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writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
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&clock_manager_base->sdr_pll_ddrdqsclk);
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writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
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&clock_manager_base->sdr_pll_ddr2xdqsclk);
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writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
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&clock_manager_base->sdr_pll_ddrdqclk);
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writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
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&clock_manager_base->sdr_pll_s2fuser2clk);
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/*
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* after locking, but before taking out of bypass
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* assert/deassert outresetall
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*/
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uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
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/* assert main outresetall */
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writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->main_pll_vco);
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uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
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/* assert pheriph outresetall */
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writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->per_pll_vco);
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/* assert sdram outresetall */
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writel(cfg->sdram_vco_base | VCO_EN_BASE|
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
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&clock_manager_base->sdr_pll_vco);
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/* deassert main outresetall */
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writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->main_pll_vco);
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/* deassert pheriph outresetall */
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writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->per_pll_vco);
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/* deassert sdram outresetall */
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writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
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cfg->sdram_vco_base | VCO_EN_BASE,
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&clock_manager_base->sdr_pll_vco);
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/*
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* now that we've toggled outreset all, all the clocks
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* are aligned nicely; so we can change any phase.
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*/
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cm_write_with_phase(cfg->ddrdqsclk,
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(uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
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CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
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/* SDRAM DDR2XDQSCLK */
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cm_write_with_phase(cfg->ddr2xdqsclk,
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(uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
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CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
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cm_write_with_phase(cfg->ddrdqclk,
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(uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
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CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
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cm_write_with_phase(cfg->s2fuser2clk,
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(uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
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CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
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/* Take all three PLLs out of bypass when safe mode is cleared. */
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cm_write_bypass(
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CLKMGR_BYPASS_PERPLLSRC_SET(
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CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
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CLKMGR_BYPASS_SDRPLLSRC_SET(
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CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
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CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
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CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
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CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
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/* clear safe mode */
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cm_write_ctrl(readl(&clock_manager_base->ctrl) |
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CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
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/*
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* now that safe mode is clear with clocks gated
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* it safe to change the source mux for the flashes the the L4_MAIN
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*/
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writel(cfg->persrc, &clock_manager_base->per_pll_src);
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writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
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/* Now ungate non-hw-managed clocks */
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writel(~0, &clock_manager_base->main_pll_en);
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writel(~0, &clock_manager_base->per_pll_en);
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writel(~0, &clock_manager_base->sdr_pll_en);
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}
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