mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 06:43:45 +09:00
116f75c7b3
In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2
Fixes: 36f50b7523 ("armv8: ls1028a: Add other serdes
protocal support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
87 lines
1.9 KiB
C
87 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS_MAX_LANES];
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u8 rcw_lanes[SRDS_MAX_LANES];
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};
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static struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
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{0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
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{0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
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{0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
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{0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
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{0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
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{0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
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{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
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{0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
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{0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
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{0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
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{0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
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{0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
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{0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
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{0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} },
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{0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
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{0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} },
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{0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} },
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{0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} },
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{0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} },
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{0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} },
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{}
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};
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static struct serdes_config *serdes_cfg_tbl[] = {
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serdes1_cfg_tbl,
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == cfg)
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return ptr->lanes[lane];
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ptr++;
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}
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return 0;
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == prtcl)
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break;
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ptr++;
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}
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if (!ptr->protocol)
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (ptr->lanes[i] != NONE)
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return 1;
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}
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return 0;
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}
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