mirror of
https://github.com/brain-hackers/u-boot-brain
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b1e6c4c3d4
Many boot image configuration files refer to the appropriate documentation file, but these references contain typos in the directory and file name. Fix them. Also fix reference to doc/README.SPL file. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
121 lines
3.0 KiB
INI
121 lines
3.0 KiB
INI
/*
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* (C) Copyright 2012
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* Stefano Babic DENX Software Engineering sbabic@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not write to the Free Software
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* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
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* MA 02110-1301 USA
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM nor
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* IOMUX for RAM only */
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DATA 4 0x53fa8554 0x300020
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DATA 4 0x53fa8560 0x300020
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DATA 4 0x53fa8594 0x300020
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DATA 4 0x53fa8584 0x300020
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DATA 4 0x53fa8558 0x300040
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DATA 4 0x53fa8568 0x300040
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DATA 4 0x53fa8590 0x300040
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DATA 4 0x53fa857c 0x300040
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DATA 4 0x53fa8564 0x300040
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DATA 4 0x53fa8580 0x300040
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DATA 4 0x53fa8570 0x300220
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DATA 4 0x53fa8578 0x300220
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DATA 4 0x53fa872c 0x300000
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DATA 4 0x53fa8728 0x300000
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DATA 4 0x53fa871c 0x300000
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DATA 4 0x53fa8718 0x300000
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DATA 4 0x53fa8574 0x300020
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DATA 4 0x53fa8588 0x300020
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DATA 4 0x53fa855c 0x0
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DATA 4 0x53fa858c 0x0
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DATA 4 0x53fa856c 0x300040
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DATA 4 0x53fa86f0 0x300000
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DATA 4 0x53fa8720 0x300000
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DATA 4 0x53fa86fc 0x0
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DATA 4 0x53fa86f4 0x0
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DATA 4 0x53fa8714 0x0
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DATA 4 0x53fa8724 0x4000000
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/* DDR RAM */
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DATA 4 0x63fd9088 0x40404040
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DATA 4 0x63fd9090 0x40404040
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DATA 4 0x63fd907C 0x01420143
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DATA 4 0x63fd9080 0x01450146
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DATA 4 0x63fd9018 0x00111740
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DATA 4 0x63fd9000 0x84190000
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/* esdcfgX */
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DATA 4 0x63fd900C 0x9f5152e3
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DATA 4 0x63fd9010 0xb68e8a63
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DATA 4 0x63fd9014 0x01ff00db
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/* Read/Write command delay */
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DATA 4 0x63fd902c 0x000026d2
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/* Out of reset delays */
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DATA 4 0x63fd9030 0x00ff0e21
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/* ESDCTL ODT timing control */
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DATA 4 0x63fd9008 0x12273030
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/* ESDCTL power down control */
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DATA 4 0x63fd9004 0x0002002d
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/* Set registers in DDR memory chips */
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DATA 4 0x63fd901c 0x00008032
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DATA 4 0x63fd901c 0x00008033
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DATA 4 0x63fd901c 0x00028031
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DATA 4 0x63fd901c 0x052080b0
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DATA 4 0x63fd901c 0x04008040
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/* ESDCTL refresh control */
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DATA 4 0x63fd9020 0x00005800
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/* PHY ZQ HW control */
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DATA 4 0x63fd9040 0x05380003
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/* PHY ODT control */
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DATA 4 0x63fd9058 0x00022222
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/* start DDR3 */
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DATA 4 0x63fd901c 0x00000000
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