mirror of
https://github.com/brain-hackers/u-boot-brain
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9199b9cc8f
This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with the DDR2 configuration to only use one CS (rank). As this code is most likely copied from the original Sequoia version, this error was copied as well. Signed-off-by: Stefan Roese <sr@denx.de>
116 lines
3.5 KiB
C
116 lines
3.5 KiB
C
/*
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* (C) Copyright 2006
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* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
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*
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debug output */
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#undef DEBUG
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <ppc440.h>
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extern int denali_wait_for_dlllock(void);
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extern void denali_core_search_data_eye(void);
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#if defined(CONFIG_NAND_SPL)
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/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
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* for the 4k NAND boot image so define bus_frequency to 133MHz here
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* which is save for the refresh counter setup.
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*/
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#define get_bus_freq(val) 133000000
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#endif
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/*************************************************************************
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*
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* initdram -- 440EPx's DDR controller is a DENALI Core
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*
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************************************************************************/
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phys_size_t initdram (int board_type)
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{
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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#if !defined(CONFIG_NAND_SPL)
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ulong speed = get_bus_freq(0);
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#else
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ulong speed = 133333333; /* 133MHz is on the safe side */
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#endif
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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mtsdram(DDR0_01, 0x01000000);
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mtsdram(DDR0_03, 0x02030602);
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mtsdram(DDR0_04, 0x0A020200);
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mtsdram(DDR0_05, 0x02020308);
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mtsdram(DDR0_06, 0x0102C812);
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mtsdram(DDR0_07, 0x000D0100);
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mtsdram(DDR0_08, 0x02430001);
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mtsdram(DDR0_09, 0x00011D5F);
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mtsdram(DDR0_10, 0x00000100);
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mtsdram(DDR0_11, 0x0027C800);
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mtsdram(DDR0_12, 0x00000003);
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mtsdram(DDR0_14, 0x00000000);
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mtsdram(DDR0_17, 0x19000000);
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mtsdram(DDR0_18, 0x19191919);
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mtsdram(DDR0_19, 0x19191919);
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mtsdram(DDR0_20, 0x0B0B0B0B);
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mtsdram(DDR0_21, 0x0B0B0B0B);
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mtsdram(DDR0_22, 0x00267F0B);
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mtsdram(DDR0_23, 0x00000000);
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mtsdram(DDR0_24, 0x01010002);
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if (speed > 133333334)
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mtsdram(DDR0_26, 0x5B26050C);
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else
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mtsdram(DDR0_26, 0x5B260408);
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mtsdram(DDR0_27, 0x0000682B);
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mtsdram(DDR0_28, 0x00000000);
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mtsdram(DDR0_31, 0x00000000);
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mtsdram(DDR0_42, 0x01000006);
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mtsdram(DDR0_43, 0x030A0200);
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mtsdram(DDR0_44, 0x00000003);
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mtsdram(DDR0_02, 0x00000001);
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denali_wait_for_dlllock();
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#endif /* #ifndef CONFIG_NAND_U_BOOT */
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#ifdef CONFIG_DDR_DATA_EYE
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/* -----------------------------------------------------------+
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* Perform data eye search if requested.
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* ----------------------------------------------------------*/
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denali_core_search_data_eye();
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#endif
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/*
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* Clear possible errors resulting from data-eye-search.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return (CONFIG_SYS_MBYTES_SDRAM << 20);
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}
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