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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
205 lines
6.4 KiB
C
205 lines
6.4 KiB
C
// SPDX-License-Identifier: Intel
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/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Ported from Intel released Quark UEFI BIOS
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* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
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*/
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/*
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* This is the main Quark Memory Reference Code (MRC)
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*
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* These functions are generic and should work for any Quark-based board.
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*
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* MRC requires two data structures to be passed in which are initialized by
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* mrc_adjust_params().
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*
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* The basic flow is as follows:
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* 01) Check for supported DDR speed configuration
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* 02) Set up Memory Manager buffer as pass-through (POR)
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* 03) Set Channel Interleaving Mode and Channel Stride to the most aggressive
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* setting possible
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* 04) Set up the Memory Controller logic
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* 05) Set up the DDR_PHY logic
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* 06) Initialise the DRAMs (JEDEC)
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* 07) Perform the Receive Enable Calibration algorithm
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* 08) Perform the Write Leveling algorithm
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* 09) Perform the Read Training algorithm (includes internal Vref)
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* 10) Perform the Write Training algorithm
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* 11) Set Channel Interleaving Mode and Channel Stride to the desired settings
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*
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* DRAM unit configuration based on Valleyview MRC.
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*/
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#include <common.h>
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#include <version.h>
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#include <asm/arch/mrc.h>
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#include <asm/arch/msg_port.h>
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#include "mrc_util.h"
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#include "smc.h"
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static const struct mem_init init[] = {
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{ 0x0101, BM_COLD | BM_FAST | BM_WARM | BM_S3, clear_self_refresh },
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{ 0x0200, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_timing_control },
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{ 0x0103, BM_COLD | BM_FAST , prog_decode_before_jedec },
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{ 0x0104, BM_COLD | BM_FAST , perform_ddr_reset },
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{ 0x0300, BM_COLD | BM_FAST | BM_S3, ddrphy_init },
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{ 0x0400, BM_COLD | BM_FAST , perform_jedec_init },
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{ 0x0105, BM_COLD | BM_FAST , set_ddr_init_complete },
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{ 0x0106, BM_FAST | BM_WARM | BM_S3, restore_timings },
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{ 0x0106, BM_COLD , default_timings },
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{ 0x0500, BM_COLD , rcvn_cal },
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{ 0x0600, BM_COLD , wr_level },
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{ 0x0120, BM_COLD , prog_page_ctrl },
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{ 0x0700, BM_COLD , rd_train },
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{ 0x0800, BM_COLD , wr_train },
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{ 0x010b, BM_COLD , store_timings },
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{ 0x010c, BM_COLD | BM_FAST | BM_WARM | BM_S3, enable_scrambling },
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{ 0x010d, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_control },
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{ 0x010e, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_dra_drb },
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{ 0x010f, BM_WARM | BM_S3, perform_wake },
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{ 0x0110, BM_COLD | BM_FAST | BM_WARM | BM_S3, change_refresh_period },
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{ 0x0111, BM_COLD | BM_FAST | BM_WARM | BM_S3, set_auto_refresh },
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{ 0x0112, BM_COLD | BM_FAST | BM_WARM | BM_S3, ecc_enable },
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{ 0x0113, BM_COLD | BM_FAST , memory_test },
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{ 0x0114, BM_COLD | BM_FAST | BM_WARM | BM_S3, lock_registers }
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};
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/* Adjust configuration parameters before initialization sequence */
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static void mrc_adjust_params(struct mrc_params *mrc_params)
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{
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const struct dram_params *dram_params;
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uint8_t dram_width;
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uint32_t rank_enables;
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uint32_t channel_width;
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ENTERFN();
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/* initially expect success */
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mrc_params->status = MRC_SUCCESS;
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dram_width = mrc_params->dram_width;
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rank_enables = mrc_params->rank_enables;
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channel_width = mrc_params->channel_width;
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/*
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* Setup board layout (must be reviewed as is selecting static timings)
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* 0 == R0 (DDR3 x16), 1 == R1 (DDR3 x16),
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* 2 == DV (DDR3 x8), 3 == SV (DDR3 x8).
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*/
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if (dram_width == X8)
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mrc_params->board_id = 2; /* select x8 layout */
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else
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mrc_params->board_id = 0; /* select x16 layout */
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/* initially no memory */
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mrc_params->mem_size = 0;
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/* begin of channel settings */
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dram_params = &mrc_params->params;
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/*
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* Determine column bits:
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*
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* Column: 11 for 8Gbx8, else 10
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*/
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mrc_params->column_bits[0] =
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(dram_params[0].density == 4) &&
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(dram_width == X8) ? 11 : 10;
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/*
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* Determine row bits:
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*
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* 512Mbx16=12 512Mbx8=13
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* 1Gbx16=13 1Gbx8=14
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* 2Gbx16=14 2Gbx8=15
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* 4Gbx16=15 4Gbx8=16
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* 8Gbx16=16 8Gbx8=16
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*/
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mrc_params->row_bits[0] = 12 + dram_params[0].density +
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(dram_params[0].density < 4) &&
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(dram_width == X8) ? 1 : 0;
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/*
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* Determine per-channel memory size:
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*
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* (For 2 RANKs, multiply by 2)
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* (For 16 bit data bus, divide by 2)
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*
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* DENSITY WIDTH MEM_AVAILABLE
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* 512Mb x16 0x008000000 ( 128MB)
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* 512Mb x8 0x010000000 ( 256MB)
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* 1Gb x16 0x010000000 ( 256MB)
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* 1Gb x8 0x020000000 ( 512MB)
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* 2Gb x16 0x020000000 ( 512MB)
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* 2Gb x8 0x040000000 (1024MB)
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* 4Gb x16 0x040000000 (1024MB)
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* 4Gb x8 0x080000000 (2048MB)
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*/
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mrc_params->channel_size[0] = 1 << dram_params[0].density;
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mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1;
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mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1;
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mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2;
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/* Determine memory size (convert number of 64MB/512Mb units) */
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mrc_params->mem_size += mrc_params->channel_size[0] << 26;
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LEAVEFN();
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}
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static void mrc_mem_init(struct mrc_params *mrc_params)
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{
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int i;
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ENTERFN();
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/* MRC started */
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mrc_post_code(0x01, 0x00);
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if (mrc_params->boot_mode != BM_COLD) {
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if (mrc_params->ddr_speed != mrc_params->timings.ddr_speed) {
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/* full training required as frequency changed */
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mrc_params->boot_mode = BM_COLD;
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}
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}
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for (i = 0; i < ARRAY_SIZE(init); i++) {
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uint64_t my_tsc;
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if (mrc_params->boot_mode & init[i].boot_path) {
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uint8_t major = init[i].post_code >> 8 & 0xff;
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uint8_t minor = init[i].post_code >> 0 & 0xff;
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mrc_post_code(major, minor);
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my_tsc = rdtsc();
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init[i].init_fn(mrc_params);
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DPF(D_TIME, "Execution time %llx", rdtsc() - my_tsc);
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}
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}
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/* display the timings */
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print_timings(mrc_params);
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/* MRC complete */
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mrc_post_code(0x01, 0xff);
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LEAVEFN();
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}
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void mrc_init(struct mrc_params *mrc_params)
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{
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ENTERFN();
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DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION,
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U_BOOT_DATE, U_BOOT_TIME);
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/* Set up the data structures used by mrc_mem_init() */
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mrc_adjust_params(mrc_params);
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/* Initialize system memory */
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mrc_mem_init(mrc_params);
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LEAVEFN();
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}
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