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https://github.com/brain-hackers/u-boot-brain
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![Alessio Centazzo](/assets/img/avatar_default.png)
This patch fixes a debug compilation error for PPC4xx platforms, all other architectures are not affected by this change. The 'handler' pointer was undefined. The fix is exercised and has effect only if DEBUG is defined. Signed-off-by: Alessio Centazzo acpatin@yahoo.com Signed-off-by: Stefan Roese <sr@denx.de>
181 lines
4.8 KiB
C
181 lines
4.8 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 (440 port)
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* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
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*
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* (C) Copyright 2003 (440GX port)
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* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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*
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* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
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* Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
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* Work supported by Qtechnology (htpp://qtec.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/interrupt.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <commproc.h>
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#if (UIC_MAX > 3)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
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UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
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#elif (UIC_MAX > 2)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
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UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
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#elif (UIC_MAX > 1)
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#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
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#else
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#define UICB0_ALL 0
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#endif
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u32 get_dcr(u16);
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DECLARE_GLOBAL_DATA_PTR;
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void pic_enable(void)
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{
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#if (UIC_MAX > 1)
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/* Install the UIC1 handlers */
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irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
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#endif
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#if (UIC_MAX > 2)
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irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
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#endif
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#if (UIC_MAX > 3)
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irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
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irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
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#endif
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}
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/* Handler for UIC interrupt */
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static void uic_interrupt(u32 uic_base, int vec_base)
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{
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u32 uic_msr;
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u32 msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = get_dcr(uic_base + UIC_MSR);
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msr_shift = uic_msr;
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vec = vec_base;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000)
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interrupt_run_handler(vec);
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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/*
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* Handle external interrupts
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*/
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void external_interrupt(struct pt_regs *regs)
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{
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u32 uic_msr;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = mfdcr(uic0msr);
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#if (UIC_MAX > 1)
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if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
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uic_interrupt(UIC1_DCR_BASE, 32);
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#endif
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#if (UIC_MAX > 2)
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if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
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uic_interrupt(UIC2_DCR_BASE, 64);
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#endif
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#if (UIC_MAX > 3)
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if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
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(UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
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uic_interrupt(UIC3_DCR_BASE, 96);
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#endif
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mtdcr(uic0sr, (uic_msr & UICB0_ALL));
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if (uic_msr & ~(UICB0_ALL))
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uic_interrupt(UIC0_DCR_BASE, 0);
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return;
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}
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void pic_irq_ack(unsigned int vec)
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{
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicsr, UIC_MASK(vec));
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1sr, UIC_MASK(vec));
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2sr, UIC_MASK(vec));
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else if (vec >= 96)
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mtdcr(uic3sr, UIC_MASK(vec));
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}
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/*
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* Install and free a interrupt handler.
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*/
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void pic_irq_enable(unsigned int vec)
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{
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
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else if (vec >= 96)
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mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
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debug("Install interrupt vector %d\n", vec);
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}
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void pic_irq_disable(unsigned int vec)
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{
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
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else if (vec >= 96)
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mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
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}
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