Simon Glass e761ecdbb8 x86: Add TSC timer ... This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>		2013-05-13 13:33:21 -07:00
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asm-offsets.c	x86: Initial commit for running as a coreboot payload	2011-12-19 13:26:15 +11:00
car.S	x86: Remove coreboot_ from file name	2012-12-06 14:30:43 -08:00
config.mk	x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctly	2012-12-06 14:30:42 -08:00
coreboot.c	x86: Implement panic output for coreboot	2013-05-13 13:33:20 -07:00
ipchecksum.c	x86: Import code from coreboot's libpayload to parse the coreboot table	2011-12-19 13:26:15 +11:00
Makefile	x86: Remove coreboot_ from file name	2012-12-06 14:30:43 -08:00
pci.c	x86: coreboot: Implement recursively scanning PCI busses	2012-11-28 11:40:05 -08:00
sdram.c	x86: Fix DRAM bank size init with generic board	2013-04-15 16:26:09 -07:00
tables.c	x86: coreboot: Decode additional coreboot sysinfo tags	2012-11-30 13:44:03 -08:00
timestamp.c	x86: Add TSC timer	2013-05-13 13:33:21 -07:00