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https://github.com/brain-hackers/u-boot-brain
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![Peter Tyser](/assets/img/avatar_default.png)
- Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
266 lines
5.9 KiB
C
266 lines
5.9 KiB
C
/*
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* Copyright 2006 Freescale Semiconductor
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <mpc86xx.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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/*
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* Default board reset function
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*/
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static void
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__board_reset(void)
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{
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/* Do nothing */
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}
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void board_reset(void) __attribute((weak, alias("__board_reset")));
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int
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checkcpu(void)
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{
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sys_info_t sysinfo;
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uint pvr, svr;
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uint ver;
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uint major, minor;
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char buf1[32], buf2[32];
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint msscr0 = mfspr(MSSCR0);
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts("CPU: ");
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switch (ver) {
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case SVR_8641:
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puts("8641");
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break;
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case SVR_8641D:
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puts("8641D");
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break;
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case SVR_8610:
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puts("8610");
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break;
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default:
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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puts("Core: ");
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pvr = get_pvr();
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ver = PVR_E600_VER(pvr);
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major = PVR_E600_MAJ(pvr);
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minor = PVR_E600_MIN(pvr);
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printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
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if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
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puts("\n Core1Translation Enabled");
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debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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get_sys_info(&sysinfo);
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puts("Clock Configuration:\n");
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printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
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printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
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printf(" DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, sysinfo.freqSystemBus / 2),
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strmhz(buf2, sysinfo.freqSystemBus));
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if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
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printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
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} else {
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printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
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sysinfo.freqLocalBus);
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}
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puts("L1: D-cache 32 KB enabled\n");
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puts(" I-cache 32 KB enabled\n");
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puts("L2: ");
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if (get_l2cr() & 0x80000000) {
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#if defined(CONFIG_MPC8610)
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puts("256");
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#elif defined(CONFIG_MPC8641)
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puts("512");
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#endif
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puts(" KB enabled\n");
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} else {
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puts("Disabled\n");
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}
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return 0;
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}
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void
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do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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/* Attempt board-specific reset */
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board_reset();
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/* Next try asserting HRESET_REQ */
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out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
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while (1)
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;
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}
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/*
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* Get timebase clock frequency
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*/
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unsigned long
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get_tbclk(void)
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{
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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return (sys_info.freqSystemBus + 3L) / 4L;
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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#if defined(CONFIG_MPC8610)
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/*
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* This actually feed the hard enabled watchdog.
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*/
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_wdt_t *wdt = &immap->im_wdt;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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u32 tmp = gur->pordevsr;
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if (tmp & 0x4000) {
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wdt->swsrr = 0x556c;
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wdt->swsrr = 0xaa39;
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}
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#endif
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}
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_DDR_ECC)
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void
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dma_init(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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dma->satr0 = 0x00040000;
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dma->datr0 = 0x00040000;
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asm("sync; isync");
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}
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uint
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dma_check(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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volatile uint status = dma->sr0;
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/* While the channel is busy, spin */
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while ((status & 4) == 4) {
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status = dma->sr0;
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}
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if (status != 0) {
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printf("DMA Error: status = %x\n", status);
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}
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return status;
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}
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int
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dma_xfer(void *dest, uint count, void *src)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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dma->dar0 = (uint) dest;
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dma->sar0 = (uint) src;
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dma->bcr0 = count;
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dma->mr0 = 0xf000004;
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asm("sync;isync");
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dma->mr0 = 0xf000005;
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asm("sync;isync");
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return dma_check();
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}
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#endif /* CONFIG_DDR_ECC */
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/*
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* Print out the state of various machine registers.
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* Currently prints out LAWs, BR0/OR0, and BATs
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*/
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void mpc86xx_reginfo(void)
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{
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immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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ccsr_lbc_t *lbc = &immap->im_lbc;
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print_bats();
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print_laws();
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printf ("Local Bus Controller Registers\n"
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"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
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printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
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printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
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printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
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printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
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printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
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printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
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printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
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}
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_TSEC_ENET)
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tsec_standard_init(bis);
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#endif
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return 0;
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}
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