mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 16:38:53 +09:00
240 lines
5.3 KiB
C
240 lines
5.3 KiB
C
/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#if defined(CONFIG_CF_DSPI)
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#include <asm/immap.h>
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void dspi_init(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
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GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
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GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
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GPIO_PAR_DSPI_SCK_SCK;
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dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
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DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
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DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
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DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
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#ifdef CONFIG_SYS_DSPI_DCTAR0
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dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
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#endif
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#ifdef CONFIG_SYS_DSPI_DCTAR1
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dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
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#endif
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#ifdef CONFIG_SYS_DSPI_DCTAR2
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dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
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#endif
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#ifdef CONFIG_SYS_DSPI_DCTAR3
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dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
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#endif
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#ifdef CONFIG_SYS_DSPI_DCTAR4
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dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
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#endif
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#ifdef CONFIG_SYS_DSPI_DCTAR5
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dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
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#endif
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#ifdef CONFIG_SYS_DSPI_DCTAR6
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dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
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#endif
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#ifdef CONFIG_SYS_DSPI_DCTAR7
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dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
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#endif
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}
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void dspi_tx(int chipsel, u8 attrib, u16 data)
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{
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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while ((dspi->dsr & 0x0000F000) >= 4) ;
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dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
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}
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u16 dspi_rx(void)
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{
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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while ((dspi->dsr & 0x000000F0) == 0) ;
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return (dspi->drfr & 0xFFFF);
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}
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#if defined(CONFIG_CMD_SPI)
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void spi_init_f(void)
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{
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}
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void spi_init_r(void)
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{
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}
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void spi_init(void)
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{
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dspi_init();
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct spi_slave *slave;
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slave = malloc(sizeof(struct spi_slave));
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if (!slave)
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return NULL;
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slave->bus = bus;
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slave->cs = cs;
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return slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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free(slave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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static int bWrite = 0;
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u8 *spi_rd, *spi_wr;
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int len = bitlen >> 3;
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spi_rd = (u8 *) din;
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spi_wr = (u8 *) dout;
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/* command handling */
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if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
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switch (*spi_wr) {
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case 0x02: /* Page Prog */
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bWrite = 1;
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dspi_tx(slave->cs, 0x80, spi_wr[0]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[1]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[2]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[3]);
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dspi_rx();
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return 0;
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case 0x05: /* Read Status */
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if (len == 4)
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if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
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&& (spi_wr[3] == 0xFF)) {
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dspi_tx(slave->cs, 0x80, *spi_wr);
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dspi_rx();
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}
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return 0;
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case 0x06: /* WREN */
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dspi_tx(slave->cs, 0x00, *spi_wr);
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dspi_rx();
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return 0;
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case 0x0B: /* Fast read */
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if ((len == 5) && (spi_wr[4] == 0)) {
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dspi_tx(slave->cs, 0x80, spi_wr[0]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[1]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[2]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[3]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[4]);
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dspi_rx();
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}
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return 0;
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case 0x9F: /* RDID */
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dspi_tx(slave->cs, 0x80, *spi_wr);
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dspi_rx();
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return 0;
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case 0xD8: /* Sector erase */
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if (len == 4)
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if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
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dspi_tx(slave->cs, 0x80, spi_wr[0]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[1]);
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dspi_rx();
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dspi_tx(slave->cs, 0x80, spi_wr[2]);
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dspi_rx();
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dspi_tx(slave->cs, 0x00, spi_wr[3]);
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dspi_rx();
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}
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return 0;
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}
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}
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if (bWrite)
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len--;
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while (len--) {
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if (dout != NULL) {
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dspi_tx(slave->cs, 0x80, *spi_wr);
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dspi_rx();
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spi_wr++;
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}
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if (din != NULL) {
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dspi_tx(slave->cs, 0x80, 0);
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*spi_rd = dspi_rx();
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spi_rd++;
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}
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}
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if (flags == SPI_XFER_END) {
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if (bWrite) {
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dspi_tx(slave->cs, 0x00, *spi_wr);
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dspi_rx();
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bWrite = 0;
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} else {
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dspi_tx(slave->cs, 0x00, 0);
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dspi_rx();
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}
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}
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return 0;
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}
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#endif /* CONFIG_CMD_SPI */
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#endif /* CONFIG_CF_DSPI */
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