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![Green Wan](/assets/img/avatar_default.png)
Add dts support for fu740. The HiFive Unmatched support is based on fu740 cpu and drivers in following patch set. Signed-off-by: Green Wan <green.wan@sifive.com> [greentime.hu: set fu740 speed to 1.2GHz] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
106 lines
2.1 KiB
Plaintext
106 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* (C) Copyright 2020-2021 SiFive, Inc
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*/
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#include <dt-bindings/reset/sifive-fu740-prci.h>
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/ {
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cpus {
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assigned-clocks = <&prci PRCI_CLK_COREPLL>;
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assigned-clock-rates = <1200000000>;
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u-boot,dm-spl;
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cpu0: cpu@0 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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status = "okay";
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cpu0_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu1: cpu@1 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu1_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu2: cpu@2 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu2_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu3: cpu@3 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu3_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu4: cpu@4 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu4_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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};
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soc {
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u-boot,dm-spl;
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clint: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
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&cpu1_intc 3 &cpu1_intc 7
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&cpu2_intc 3 &cpu2_intc 7
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&cpu3_intc 3 &cpu3_intc 7
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&cpu4_intc 3 &cpu4_intc 7>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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u-boot,dm-spl;
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};
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prci: clock-controller@10000000 {
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#reset-cells = <1>;
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resets = <&prci PRCI_RST_DDR_CTRL_N>,
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<&prci PRCI_RST_DDR_AXI_N>,
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<&prci PRCI_RST_DDR_AHB_N>,
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<&prci PRCI_RST_DDR_PHY_N>,
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<&prci PRCI_RST_GEMGXL_N>,
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<&prci PRCI_RST_CLTX_N>;
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reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
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"ddr_phy", "gemgxl_reset", "cltx_reset";
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};
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dmc: dmc@100b0000 {
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compatible = "sifive,fu740-c000-ddr";
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reg = <0x0 0x100b0000 0x0 0x0800
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0x0 0x100b2000 0x0 0x2000
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0x0 0x100b8000 0x0 0x1000>;
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clocks = <&prci PRCI_CLK_DDRPLL>;
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clock-frequency = <933333324>;
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u-boot,dm-spl;
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};
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};
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};
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&prci {
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u-boot,dm-spl;
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};
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&uart0 {
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u-boot,dm-spl;
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};
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&spi0 {
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u-boot,dm-spl;
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};
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ð0 {
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assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
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assigned-clock-rates = <125125000>;
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};
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&ccache {
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status = "okay";
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};
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