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https://github.com/brain-hackers/u-boot-brain
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![Guillaume GARDET](/assets/img/avatar_default.png)
Boot tested on sabrelite board. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Gary Bisson <gary.bisson@boundarydevices.com> Tested-by: Denis Pynkin <denis.pynkin@collabora.com>
186 lines
4.7 KiB
C
186 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Boundary Devices Nitrogen6X
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* and Freescale i.MX6Q Sabre Lite boards.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "mx6_common.h"
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#define CONFIG_MACH_TYPE 3769
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_USBD_HS
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#define CONFIG_NETCONSOLE
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART2_BASE
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#ifdef CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_SPEED 25000000
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#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
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#endif
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_I2C_EDID
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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/*
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* SATA Configs
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*/
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#ifdef CONFIG_CMD_SATA
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#define CONFIG_SYS_SATA_MAX_DEVICE 1
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#define CONFIG_DWC_AHSATA_PORT_ID 0
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#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
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#define CONFIG_LBA48
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#endif
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 6
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/* USB Configs */
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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/* Framebuffer and LCD */
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_VIDEO_BMP_GZIP
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
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#define CONFIG_BMP_16BPP
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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#define CONFIG_PREBOOT ""
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#ifdef CONFIG_CMD_MMC
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#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
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#else
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#define DISTRO_BOOT_DEV_MMC(func)
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#endif
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#ifdef CONFIG_CMD_SATA
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#define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0)
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#else
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#define DISTRO_BOOT_DEV_SATA(func)
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#endif
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#ifdef CONFIG_USB_STORAGE
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#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
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#else
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#define DISTRO_BOOT_DEV_USB(func)
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#endif
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#ifdef CONFIG_CMD_PXE
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#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
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#else
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#define DISTRO_BOOT_DEV_PXE(func)
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#endif
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#ifdef CONFIG_CMD_DHCP
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#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
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#else
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#define DISTRO_BOOT_DEV_DHCP(func)
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#endif
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#if defined(CONFIG_SABRELITE)
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#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0"
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#else
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/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */
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#define FDTFILE
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#endif
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#define BOOT_TARGET_DEVICES(func) \
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DISTRO_BOOT_DEV_MMC(func) \
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DISTRO_BOOT_DEV_SATA(func) \
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DISTRO_BOOT_DEV_USB(func) \
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DISTRO_BOOT_DEV_PXE(func) \
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DISTRO_BOOT_DEV_DHCP(func)
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console=ttymxc1\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_addr_r=0x18000000\0" \
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FDTFILE \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
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"ramdisk_addr_r=0x13000000\0" \
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"ramdiskaddr=0x13000000\0" \
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"ip_dyn=yes\0" \
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"usb_pgood_delay=2000\0" \
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BOOTENV
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_MEMTEST_START 0x10000000
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#define CONFIG_SYS_MEMTEST_END 0x10010000
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#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* Environment organization */
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#define CONFIG_ENV_SIZE (8 * 1024)
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#if defined(CONFIG_ENV_IS_IN_MMC)
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
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#define CONFIG_ENV_OFFSET (768 * 1024)
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#define CONFIG_ENV_SECT_SIZE (8 * 1024)
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#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
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#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
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#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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#endif
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/*
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* PCI express
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*/
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#ifdef CONFIG_CMD_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCIE_IMX
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#endif
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#endif /* __CONFIG_H */
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