mirror of
https://github.com/brain-hackers/u-boot-brain
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02cd449f0b
This patch rewrites the mtmips architecture with the following changes: 1. Move MT7628 soc parts into a subfolder. 2. Lock parts of D-Cache as temporary stack. 3. Reimplement DDR initialization in C language. 4. Reimplement DDR calibration in a clear logic. 5. Add full support for auto size detection for DDR1 and DDR2. 6. Use accurate CPU clock depending on the input xtal frequency for timer and delay functions. Note: print_cpuinfo() has incompatible parts with MT7620 so it's moved into mt7628 subfolder. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
110 lines
2.4 KiB
C
110 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/mt7628-clk.h>
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#include <linux/io.h>
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#include "mt7628.h"
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DECLARE_GLOBAL_DATA_PTR;
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static void set_init_timer_freq(void)
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{
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void __iomem *sysc;
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u32 bs, val, timer_freq_post;
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sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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/* We can't use the clk driver as the DM has not been initialized yet */
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bs = readl(sysc + SYSCTL_SYSCFG0_REG);
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if ((bs & XTAL_FREQ_SEL) == XTAL_25MHZ) {
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gd->arch.timer_freq = 25000000;
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timer_freq_post = 575000000;
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} else {
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gd->arch.timer_freq = 40000000;
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timer_freq_post = 580000000;
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}
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val = readl(sysc + SYSCTL_CLKCFG0_REG);
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if (!(val & (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)))
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gd->arch.timer_freq = timer_freq_post;
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}
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void mt7628_init(void)
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{
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set_init_timer_freq();
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mt7628_ddr_init();
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}
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int print_cpuinfo(void)
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{
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void __iomem *sysc;
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struct udevice *clkdev;
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u32 val, ver, eco, pkg, ddr, chipmode, ee;
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ulong cpu_clk, bus_clk, xtal_clk, timer_freq;
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struct clk clk;
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int ret;
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sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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val = readl(sysc + SYSCTL_CHIP_REV_ID_REG);
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ver = (val & VER_M) >> VER_S;
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eco = (val & ECO_M) >> ECO_S;
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pkg = !!(val & PKG_ID);
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val = readl(sysc + SYSCTL_SYSCFG0_REG);
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ddr = val & DRAM_TYPE;
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chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S;
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val = readl(sysc + SYSCTL_EFUSE_CFG_REG);
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ee = val & EFUSE_MT7688;
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printf("CPU: MediaTek MT%u%c ver:%u eco:%u\n",
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ee ? 7688 : 7628, pkg ? 'A' : 'K', ver, eco);
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printf("Boot: DDR%s, SPI-NOR %u-Byte Addr, CPU clock from %s\n",
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ddr ? "" : "2", chipmode & 0x01 ? 4 : 3,
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chipmode & 0x02 ? "XTAL" : "CPLL");
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ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(mt7628_clk),
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&clkdev);
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if (ret)
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return ret;
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clk.dev = clkdev;
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clk.id = CLK_CPU;
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cpu_clk = clk_get_rate(&clk);
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clk.id = CLK_SYS;
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bus_clk = clk_get_rate(&clk);
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clk.id = CLK_XTAL;
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xtal_clk = clk_get_rate(&clk);
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clk.id = CLK_MIPS_CNT;
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timer_freq = clk_get_rate(&clk);
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/* Set final timer frequency */
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if (timer_freq)
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gd->arch.timer_freq = timer_freq;
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printf("Clock: CPU: %luMHz, Bus: %luMHz, XTAL: %luMHz\n",
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cpu_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000);
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return 0;
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}
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ulong notrace get_tbclk(void)
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{
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return gd->arch.timer_freq;
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}
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