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https://github.com/brain-hackers/u-boot-brain
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a60c1e6d6b
SoCs of mtmips can use different CPU frequencies depending on the HW/SW configurations. For example mt7628 uses 580MHz clock if the input xtal frequency is 40MHz, and 575MHz clock if the xtal is 25MHz. Upon cold boot the CPU uses the xtal frequency directly. So hardcoding the timer frequency (half of the CPU frequency) in CONFIG_SYS_MIPS_TIMER_FREQ is not a good idea for this case. This patch adds a mtmips-specific field timer_freq to arch_global_data. This field will be used later in mtmips-specific get_tbclk() to provide accurate timer frequency in different boot stage. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
40 lines
831 B
C
40 lines
831 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#include <asm/regdef.h>
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/* Architecture-specific global data */
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struct arch_global_data {
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#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
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unsigned long io_port_base;
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#endif
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#ifdef CONFIG_ARCH_ATH79
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unsigned long id;
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unsigned long soc;
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unsigned long rev;
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unsigned long ver;
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#endif
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#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
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unsigned short l1i_line_size;
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unsigned short l1d_line_size;
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#endif
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#ifdef CONFIG_MIPS_L2_CACHE
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unsigned short l2_line_size;
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#endif
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#ifdef CONFIG_ARCH_MTMIPS
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unsigned long timer_freq;
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#endif
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};
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#include <asm-generic/global_data.h>
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
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#endif /* __ASM_GBL_DATA_H */
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