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https://github.com/brain-hackers/u-boot-brain
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e8e39597a3
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok. Detail verification message please see doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
70 lines
996 B
Plaintext
70 lines
996 B
Plaintext
/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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OUTPUT_ARCH("riscv")
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ENTRY(_start)
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SECTIONS
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{
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. = ALIGN(4);
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.text :
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{
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arch/riscv/cpu/nx25/start.o (.text)
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*(.text)
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}
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
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. = ALIGN(4);
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.data : {
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__global_pointer$ = . + 0x800;
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*(.data*)
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}
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. = ALIGN(4);
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.got : {
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__got_start = .;
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*(.got.plt) *(.got)
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__got_end = .;
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}
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*)));
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}
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. = ALIGN(4);
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/DISCARD/ : { *(.rela.plt*) }
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.rela.dyn : {
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__rel_dyn_start = .;
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*(.rela*)
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__rel_dyn_end = .;
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}
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. = ALIGN(4);
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.dynsym : {
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__dyn_sym_start = .;
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*(.dynsym)
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__dyn_sym_end = .;
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}
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. = ALIGN(4);
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_end = .;
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.bss : {
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__bss_start = .;
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*(.bss)
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. = ALIGN(4);
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__bss_end = .;
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}
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}
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