mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
156 lines
3.0 KiB
C
156 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 Toradex
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8-pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <env.h>
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#include <errno.h>
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#include <linux/libfdt.h>
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#include "../common/tdx-cfg-block.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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static iomux_cfg_t uart1_pads[] = {
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SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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void board_mem_get_layout(u64 *phys_sdram_1_start,
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u64 *phys_sdram_1_size,
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u64 *phys_sdram_2_start,
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u64 *phys_sdram_2_size)
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{
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u32 is_dualx = 0, val = 0;
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sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
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if (scierr == SC_ERR_NONE) {
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/* DX has two A35 cores disabled */
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is_dualx = (val & 0xf) != 0x0;
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}
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*phys_sdram_1_start = PHYS_SDRAM_1;
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if (is_dualx)
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/* Our DX based SKUs only have 1 GB RAM */
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*phys_sdram_1_size = SZ_1G;
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else
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*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
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*phys_sdram_2_start = PHYS_SDRAM_2;
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*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
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}
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int board_early_init_f(void)
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{
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sc_pm_clock_rate_t rate;
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sc_err_t err = 0;
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/*
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* This works around that having only UART3 up the baudrate is 1.2M
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* instead of 115.2k. Set UART0 clock root to 80 MHz
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*/
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rate = 80000000;
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err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
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if (err != SC_ERR_NONE)
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return 0;
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/* Set UART3 clock root to 80 MHz and enable it */
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rate = SC_80MHZ;
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err = sc_pm_setup_uart(SC_R_UART_1, rate);
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if (err != SC_ERR_NONE)
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return 0;
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setup_iomux_uart();
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return 0;
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}
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#if IS_ENABLED(CONFIG_DM_GPIO)
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static void board_gpio_init(void)
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{
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/* TODO */
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}
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#else
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static inline void board_gpio_init(void) {}
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#endif
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#if IS_ENABLED(CONFIG_FEC_MXC)
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#include <miiphy.h>
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int checkboard(void)
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{
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puts("Model: Toradex Apalis iMX8X\n");
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build_info();
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print_bootinfo();
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return 0;
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}
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int board_init(void)
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{
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board_gpio_init();
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return 0;
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}
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/*
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* Board specific reset that is system reset.
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*/
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void reset_cpu(ulong addr)
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{
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/* TODO */
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return ft_common_board_setup(blob, bd);
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}
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#endif
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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/* TODO move to common */
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env_set("board_name", "Apalis iMX8X");
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#endif
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return 0;
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}
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