mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 14:53:44 +09:00
d64ee908a1
The PCIe bus that the ULI M1575 is connected to has no possible way of needing more than the fixed amount of IO & Memory space needed by the ULI. So make it use far less IO & memory space and have it use the shared LAW. This free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed by each bus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
243 lines
6.9 KiB
ArmAsm
243 lines
6.9 KiB
ArmAsm
/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc85xx.h>
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#define LAWAR_TRGT_PCI1 0x00000000
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#define LAWAR_TRGT_PCIE1 0x00200000
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#define LAWAR_TRGT_PCIE2 0x00100000
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#define LAWAR_TRGT_PCIE3 0x00300000
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#define LAWAR_TRGT_LBC 0x00400000
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#define LAWAR_TRGT_DDR 0x00f00000
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/*
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* TLB0 and TLB1 Entries
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*
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* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
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* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
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* these TLB entries are established.
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*
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* The TLB entries for DDR are dynamically setup in spd_sdram()
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* and use TLB1 Entries 8 through 15 as needed according to the
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* size of DDR memory.
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*
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* MAS0: tlbsel, esel, nv
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* MAS1: valid, iprot, tid, ts, tsize
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* MAS2: epn, sharen, x0, x1, w, i, m, g, e
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* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
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*/
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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.section .bootpg, "ax"
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.globl tlb1_entry
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tlb1_entry:
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entry_start
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/*
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* Number of TLB0 and TLB1 entries in the following table
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*/
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.long (2f-1f)/16
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1:
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/*
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* TLB0 4K Non-cacheable, guarded
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* 0xff700000 4K Initial CCSRBAR mapping
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*
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* This ends up at a TLB0 Index==0 entry, and must not collide
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* with other TLB0 Entries.
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*/
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB0 16K Cacheable, guarded
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* Temporary Global data for initialization
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*
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* Use four 4K TLB0 entries. These entries must be cacheable
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* as they provide the bootstrap memory before the memory
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* controler and real memory have been configured.
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*
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* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
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* and must not collide with other TLB0 entries.
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*/
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
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0,0,0,0,0,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
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0,0,0,0,0,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
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0,0,0,0,0,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
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0,0,0,0,0,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 0: 64M Non-cacheable, guarded
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* 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
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* Out of reset this entry is only 4K.
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*/
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.long TLB1_MAS0(1, 0, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 1: 1G Non-cacheable, guarded
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* 0x80000000 1G PCIE 8,9,a,b
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*/
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.long TLB1_MAS0(1, 1, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),
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0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),
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0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 2: 256M Non-cacheable, guarded
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*/
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.long TLB1_MAS0(1, 2, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),
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0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 3: 256M Non-cacheable, guarded
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*/
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.long TLB1_MAS0(1, 3, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),
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0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS + 0x10000000),
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0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 4: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe100_0000 255M PCI IO range
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*/
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.long TLB1_MAS0(1, 4, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
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#ifdef CFG_LBC_CACHE_BASE
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/*
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* TLB 5: 64M Cacheable, non-guarded
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*/
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.long TLB1_MAS0(1, 5, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
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#endif
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/*
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* TLB 6: 64M Non-cacheable, guarded
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* 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
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*/
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.long TLB1_MAS0(1, 6, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
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2:
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entry_end
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/*
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* LAW(Local Access Window) configuration:
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*
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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* LAW 0 is reserved for boot mapping
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*/
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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entry_start
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.long (4f-3f)/8
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3:
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.long 0
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.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
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.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
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.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
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.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
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.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
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.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
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.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
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.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
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/* contains both PCIE3 MEM & IO space */
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.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M)
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4:
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entry_end
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