mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 14:53:44 +09:00
f2cff6b104
Make the early L1 cache stack region guarded to prevent speculative fetches outside the locked range. Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. init.S whitespace cleanup. Allow TEXT_BASE value to be specified on command line. This allows it to be set to 0xfffc0000 which cuts the uboot binary in half. Clear and enable lbc and ecm errors. Update last_busno in device-tree for pci and pcie. Remove load of obsolete cpu/mpc85xx/pci.0 Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
271 lines
8.0 KiB
ArmAsm
271 lines
8.0 KiB
ArmAsm
/*
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* Copyright 2004, 2007 Freescale Semiconductor.
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* Copyright 2002,2003, Motorola Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc85xx.h>
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#define LAWAR_TRGT_PCI1 0x00000000
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#define LAWAR_TRGT_PCI2 0x00100000
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#define LAWAR_TRGT_PCIE 0x00200000
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#define LAWAR_TRGT_RIO 0x00c00000
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#define LAWAR_TRGT_LBC 0x00400000
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#define LAWAR_TRGT_DDR 0x00f00000
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/*
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* TLB0 and TLB1 Entries
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*
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* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
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* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
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* these TLB entries are established.
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*
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* The TLB entries for DDR are dynamically setup in spd_sdram()
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* and use TLB1 Entries 8 through 15 as needed according to the
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* size of DDR memory.
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*
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* MAS0: tlbsel, esel, nv
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* MAS1: valid, iprot, tid, ts, tsize
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* MAS2: epn, sharen, x0, x1, w, i, m, g, e
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* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
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*/
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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.section .bootpg, "ax"
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.globl tlb1_entry
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tlb1_entry:
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entry_start
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/*
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* Number of TLB0 and TLB1 entries in the following table
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*/
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.long (2f-1f)/16
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1:
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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/*
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* TLB0 4K Non-cacheable, guarded
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* 0xff700000 4K Initial CCSRBAR mapping
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*
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* This ends up at a TLB0 Index==0 entry, and must not collide
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* with other TLB0 Entries.
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*/
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
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#else
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#error("Update the number of table entries in tlb1_entry")
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#endif
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/*
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* TLB0 16K Cacheable, guarded
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* Temporary Global data for initialization
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*
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* Use four 4K TLB0 entries. These entries must be cacheable
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* as they provide the bootstrap memory before the memory
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* controler and real memory have been configured.
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*
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* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
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* and must not collide with other TLB0 entries.
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*/
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
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0,0,0,0,0,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
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0,0,0,0,0,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
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0,0,0,0,0,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
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0,0,0,0,0,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 0: 16M Non-cacheable, guarded
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* 0xff000000 16M FLASH
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* Out of reset this entry is only 4K.
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*/
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.long TLB1_MAS0(1, 0, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 1: 1G Non-cacheable, guarded
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* 0x80000000 1G PCI1/PCIE 8,9,a,b
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*/
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.long TLB1_MAS0(1, 1, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
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#ifdef CFG_RIO_MEM_PHYS
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/*
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* TLB 2: 256M Non-cacheable, guarded
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*/
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.long TLB1_MAS0(1, 2, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
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0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 3: 256M Non-cacheable, guarded
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*/
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.long TLB1_MAS0(1, 3, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
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0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
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0,0,0,0,0,1,0,1,0,1)
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#endif
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/*
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* TLB 5: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe200_0000 1M PCI1 IO
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* 0xe210_0000 1M PCI2 IO
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* 0xe300_0000 1M PCIe IO
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*/
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.long TLB1_MAS0(1, 5, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 6: 64M Cacheable, non-guarded
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* 0xf000_0000 64M LBC SDRAM
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*/
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.long TLB1_MAS0(1, 6, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 7: 64M Non-cacheable, guarded
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* 0xf8000000 64M CADMUS registers, relocated L2SRAM
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*/
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.long TLB1_MAS0(1, 7, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
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2:
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entry_end
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
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* 0xc000_0000 0xdfff_ffff RapidIO 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe10f_ffff PCI1 IO 1M
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* 0xe280_0000 0xe20f_ffff PCI2 IO 1M
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* 0xe300_0000 0xe30f_ffff PCIe IO 1M
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* 0xf000_0000 0xf3ff_ffff SDRAM 64M
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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* LAW 0 is reserved for boot mapping
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*/
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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entry_start
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.long (4f-3f)/8
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3:
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.long 0
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.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
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#ifdef CFG_PCI1_MEM_PHYS
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.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
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.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
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#endif
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#ifdef CFG_PCI2_MEM_PHYS
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.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
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.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
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#endif
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#ifdef CFG_PCIE1_MEM_PHYS
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.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
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.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
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#endif
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
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#ifdef CFG_RIO_MEM_PHYS
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.long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
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.long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
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#endif
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4:
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entry_end
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