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https://github.com/brain-hackers/u-boot-brain
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52923c6db7
AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
96 lines
1.4 KiB
C
96 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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void icache_enable(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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#ifdef CONFIG_RISCV_NDS
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"ori t0, t1, 0x1\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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}
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void icache_disable(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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#ifdef CONFIG_RISCV_NDS
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asm volatile (
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"fence.i\n\t"
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"csrr t1, mcache_ctl\n\t"
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"andi t0, t1, ~0x1\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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}
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void dcache_enable(void)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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#ifdef CONFIG_RISCV_NDS
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"ori t0, t1, 0x2\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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}
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void dcache_disable(void)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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#ifdef CONFIG_RISCV_NDS
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asm volatile (
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"fence\n\t"
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"csrr t1, mcache_ctl\n\t"
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"andi t0, t1, ~0x2\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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}
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int icache_status(void)
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{
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int ret = 0;
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#ifdef CONFIG_RISCV_NDS
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"andi %0, t1, 0x01\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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#endif
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return ret;
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}
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int dcache_status(void)
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{
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int ret = 0;
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#ifdef CONFIG_RISCV_NDS
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"andi %0, t1, 0x02\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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#endif
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return ret;
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}
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