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AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
8 lines
226 B
Plaintext
8 lines
226 B
Plaintext
config RISCV_NDS
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bool "AndeStar V5 ISA support"
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default n
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help
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Say Y here if you plan to run U-Boot on AndeStar v5
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platforms and use some specific features which are
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provided by Andes Technology AndeStar V5 Families.
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