mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
03544c6640
The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel. Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are. To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC. Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
73 lines
1.9 KiB
C
73 lines
1.9 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX6Q SabreSD board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX6QSABRESD_CONFIG_H
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#define __MX6QSABRESD_CONFIG_H
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#ifdef CONFIG_SPL
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#include "imx6_spl.h"
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#endif
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#define CONFIG_MACH_TYPE 3980
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_CONSOLE_DEV "ttymxc0"
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#define CONFIG_MMCROOT "/dev/mmcblk1p2"
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#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
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#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
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#include "mx6sabre_common.h"
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#define CONFIG_SYS_FSL_USDHC_NUM 3
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#if defined(CONFIG_ENV_IS_IN_MMC)
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#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
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#endif
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#define CONFIG_CMD_PCI
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#ifdef CONFIG_CMD_PCI
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCIE_IMX
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#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
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#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
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#endif
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/* I2C Configs */
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_SPEED 100000
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/* PMIC */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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/* USB Configs */
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#define CONFIG_CMD_USB
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_MX6
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#define CONFIG_USB_STORAGE
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
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#endif
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#endif /* __MX6QSABRESD_CONFIG_H */
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