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https://github.com/brain-hackers/u-boot-brain
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![Peter Tyser](/assets/img/avatar_default.png)
PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
208 lines
5.5 KiB
C
208 lines
5.5 KiB
C
/*
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* (C) Copyright 2007
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* Eran Liberty, Extricom , eran.liberty@gmail.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h> /* core U-Boot definitions */
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#include <altera.h>
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int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
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int isSerial, int isSecure);
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int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
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/****************************************************************/
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/* Stratix II Generic Implementation */
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int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case passive_serial:
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ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0);
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break;
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case fast_passive_parallel:
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ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0);
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break;
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case fast_passive_parallel_security:
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ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1);
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break;
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/* Add new interface types here */
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default:
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printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
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desc->iface);
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}
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return ret_val;
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}
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int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case passive_serial:
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case fast_passive_parallel:
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case fast_passive_parallel_security:
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ret_val = StratixII_ps_fpp_dump (desc, buf, bsize);
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break;
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/* Add new interface types here */
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default:
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printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
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desc->iface);
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}
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return ret_val;
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}
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int StratixII_info (Altera_desc * desc)
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{
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return FPGA_SUCCESS;
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}
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int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize)
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{
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printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
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return FPGA_FAIL;
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}
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int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
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int isSerial, int isSecure)
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{
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altera_board_specific_func *fns;
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int cookie;
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int ret_val = FPGA_FAIL;
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int bytecount;
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char *buff = buf;
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int i;
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if (!desc) {
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printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__);
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return FPGA_FAIL;
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}
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if (!buff) {
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printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__);
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return FPGA_FAIL;
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}
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if (!bsize) {
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printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__);
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return FPGA_FAIL;
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}
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if (!desc->iface_fns) {
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printf
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("%s(%d) Altera_desc function interface table is missing\n",
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__FUNCTION__, __LINE__);
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return FPGA_FAIL;
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}
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fns = (altera_board_specific_func *) (desc->iface_fns);
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cookie = desc->cookie;
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if (!
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(fns->config && fns->status && fns->done && fns->data
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&& fns->abort)) {
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printf
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("%s(%d) Missing some function in the function interface table\n",
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__FUNCTION__, __LINE__);
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return FPGA_FAIL;
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}
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/* 1. give board specific a chance to do anything before we start */
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if (fns->pre) {
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if ((ret_val = fns->pre (cookie)) < 0) {
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return ret_val;
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}
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}
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/* from this point on we must fail gracfully by calling lower layer abort */
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/* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
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fns->config (0, 1, cookie);
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udelay (5); /* nCONFIG low pulse width 2usec */
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fns->config (1, 1, cookie);
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udelay (100); /* nCONFIG high to first rising edge on DCLK */
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/* 3. Start the Data cycle with clk deasserted */
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bytecount = 0;
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fns->clk (0, 1, cookie);
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printf ("loading to fpga ");
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while (bytecount < bsize) {
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/* 3.1 check stratix has not signaled us an error */
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if (fns->status (cookie) != 1) {
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printf
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("\n%s(%d) Stratix failed (byte transfered till failure 0x%x)\n",
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__FUNCTION__, __LINE__, bytecount);
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fns->abort (cookie);
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return FPGA_FAIL;
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}
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if (isSerial) {
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int i;
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uint8_t data = buff[bytecount++];
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for (i = 0; i < 8; i++) {
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/* 3.2(ps) put data on the bus */
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fns->data ((data >> i) & 1, 1, cookie);
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/* 3.3(ps) clock once */
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fns->clk (1, 1, cookie);
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fns->clk (0, 1, cookie);
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}
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} else {
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/* 3.2(fpp) put data on the bus */
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fns->data (buff[bytecount++], 1, cookie);
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/* 3.3(fpp) clock once */
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fns->clk (1, 1, cookie);
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fns->clk (0, 1, cookie);
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/* 3.4(fpp) for secure cycle push 3 more clocks */
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for (i = 0; isSecure && i < 3; i++) {
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fns->clk (1, 1, cookie);
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fns->clk (0, 1, cookie);
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}
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}
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/* 3.5 while clk is deasserted it is safe to print some progress indication */
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if ((bytecount % (bsize / 100)) == 0) {
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printf ("\b\b\b%02d\%", bytecount * 100 / bsize);
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}
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}
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/* 4. Set one last clock and check conf done signal */
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fns->clk (1, 1, cookie);
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udelay (100);
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if (!fns->done (cookie)) {
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printf (" error!.\n");
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fns->abort (cookie);
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return FPGA_FAIL;
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} else {
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printf ("\b\b\b done.\n");
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}
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/* 5. call lower layer post configuration */
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if (fns->post) {
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if ((ret_val = fns->post (cookie)) < 0) {
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fns->abort (cookie);
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return ret_val;
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}
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}
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return FPGA_SUCCESS;
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}
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