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https://github.com/brain-hackers/u-boot-brain
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5d812b8b4a
Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. To support such configurations, we "only" map the first 2GB via the TLB's. We need some free virtual address space for the remaining peripherals like, SoC devices, FLASH etc. Note that ECC is currently not supported on configurations with more than 2GB SDRAM. This is because we only map the first 2GB on such systems, and therefore the ECC parity byte of the remaining area can't be written. Signed-off-by: Stefan Roese <sr@denx.de>
338 lines
12 KiB
C
338 lines
12 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* katmai.h - configuration for AMCC Katmai (440SPe)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_KATMAI 1 /* Board is Katmai */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_440SPE 1 /* Specifc SPe support */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
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/*
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* Enable this board for more than 2GB of SDRAM
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*/
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#define CONFIG_PHYS_64BIT
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME katmai
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */
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#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
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#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
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#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
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#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
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#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
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#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
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#define CFG_PCIE0_CFGBASE 0xc0000000
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#define CFG_PCIE1_CFGBASE 0xc1000000
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#define CFG_PCIE2_CFGBASE 0xc2000000
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#define CFG_PCIE0_XCFGBASE 0xc3000000
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#define CFG_PCIE1_XCFGBASE 0xc3001000
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#define CFG_PCIE2_XCFGBASE 0xc3002000
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/* base address of inbound PCIe window */
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#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
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#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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#define CFG_TEMP_STACK_OCM 1
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#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
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#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CONFIG_UART1_CONSOLE
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#undef CFG_EXT_SERIAL_CLOCK
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
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#define CONFIG_DDR_ECC 1 /* with ECC support */
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#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
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#undef CONFIG_STRESS
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */
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#define IIC0_BOOTPROM_ADDR 0x50
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#define IIC0_ALT_BOOTPROM_ADDR 0x54
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_I2C_EEPROM_ADDR (0x50)
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C RTC */
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#define CONFIG_RTC_M41T11 1
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#define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */
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#define CFG_I2C_RTC_ADDR 0x68
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#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */
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/* I2C DTT */
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#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
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#define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */
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/*
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* standard dtt sensor configuration - bottom bit will determine local or
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* remote sensor of the ADM1021, the rest determines index into
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* CFG_DTT_ADM1021 array below.
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*/
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#define CONFIG_DTT_SENSORS { 0, 1 }
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/*
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* ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
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* there will be one entry in this array for each two (dummy) sensors in
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* CONFIG_DTT_SENSORS.
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*
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* For Katmai board:
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* - only one ADM1021
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* - i2c addr 0x18
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* - conversion rate 0x02 = 0.25 conversions/second
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* - ALERT ouput disabled
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* - local temp sensor enabled, min set to 0 deg, max set to 85 deg
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* - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
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*/
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#define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_PPC_OLD \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fff10000\0" \
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"ramdisk_addr=fff20000\0" \
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"kozio=bootm ffc60000\0" \
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"pciconfighost=1\0" \
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"pcie_mode=RP:RP:RP\0" \
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""
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SNTP
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#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
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#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
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#define CONFIG_HAS_ETH0
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_RESET_DELAY 1000
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#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT /* let board init pci target */
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#undef CFG_PCI_MASTER_INIT
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#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
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/*
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* NETWORK Support (PCI):
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*/
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/* Support for Intel 82557/82559/82559ER chips. */
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#define CONFIG_EEPRO100
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/*-----------------------------------------------------------------------
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* Xilinx System ACE support
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*----------------------------------------------------------------------*/
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#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
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#define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
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#define CFG_SYSTEMACE_BASE CFG_ACE_BASE
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#define CONFIG_DOS_PARTITION 1
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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/* Memory Bank 0 (Flash) initialization */
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#define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(7) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | \
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EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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#define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \
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EBC_BXCR_BS_16MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_16BIT)
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/* Memory Bank 1 (Xilinx System ACE controller) initialization */
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#define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(4) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | \
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EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_NONDELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
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EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_16BIT)
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/*-------------------------------------------------------------------------
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* Initialize EBC CONFIG -
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* Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
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* default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
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*-------------------------------------------------------------------------*/
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#define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \
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EBC_CFG_PTD_ENABLE | \
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EBC_CFG_RTC_16PERCLK | \
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EBC_CFG_ATC_PREVIOUS | \
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EBC_CFG_DTC_PREVIOUS | \
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EBC_CFG_CTC_PREVIOUS | \
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EBC_CFG_OEO_PREVIOUS | \
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EBC_CFG_EMC_DEFAULT | \
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EBC_CFG_PME_DISABLE | \
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EBC_CFG_PR_16)
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/*-----------------------------------------------------------------------
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* GPIO Setup
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*----------------------------------------------------------------------*/
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#define CFG_GPIO_PCIE_PRESENT0 17
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#define CFG_GPIO_PCIE_PRESENT1 21
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#define CFG_GPIO_PCIE_PRESENT2 23
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#define CFG_GPIO_RS232_FORCEOFF 30
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#define CFG_PFC0 (GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \
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GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \
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GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \
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GPIO_VAL(CFG_GPIO_RS232_FORCEOFF))
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#define CFG_GPIO_OR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
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#define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
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#define CFG_GPIO_ODR 0
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#endif /* __CONFIG_H */
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