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![Stephen Warren](/assets/img/avatar_default.png)
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
237 lines
5.6 KiB
C
237 lines
5.6 KiB
C
/*
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* Samsung Exynos7420 clock driver.
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* Copyright (C) 2016 Samsung Electronics
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* Thomas Abraham <thomas.ab@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <clk-uclass.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/exynos7420-clk.h>
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#include "clk-pll.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DIVIDER(reg, shift, mask) \
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(((readl(reg) >> shift) & mask) + 1)
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/* CMU TOPC block device structure */
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struct exynos7420_clk_cmu_topc {
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unsigned int rsvd1[68];
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unsigned int bus0_pll_con[2];
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unsigned int rsvd2[2];
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unsigned int bus1_pll_con[2];
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unsigned int rsvd3[54];
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unsigned int mux_sel[6];
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unsigned int rsvd4[250];
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unsigned int div[4];
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};
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/* CMU TOP0 block device structure */
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struct exynos7420_clk_cmu_top0 {
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unsigned int rsvd0[128];
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unsigned int mux_sel[7];
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unsigned int rsvd1[261];
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unsigned int div_peric[5];
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};
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/**
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* struct exynos7420_clk_topc_priv - private data for CMU topc clock driver.
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*
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* @topc: base address of the memory mapped CMU TOPC controller.
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* @fin_freq: frequency of the Oscillator clock.
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* @sclk_bus0_pll_a: frequency of sclk_bus0_pll_a clock.
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* @sclk_bus1_pll_a: frequency of sclk_bus1_pll_a clock.
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*/
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struct exynos7420_clk_topc_priv {
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struct exynos7420_clk_cmu_topc *topc;
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unsigned long fin_freq;
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unsigned long sclk_bus0_pll_a;
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unsigned long sclk_bus1_pll_a;
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};
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/**
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* struct exynos7420_clk_top0_priv - private data for CMU top0 clock driver.
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*
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* @top0: base address of the memory mapped CMU TOP0 controller.
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* @mout_top0_bus0_pll_half: frequency of mout_top0_bus0_pll_half clock
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* @sclk_uart2: frequency of sclk_uart2 clock.
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*/
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struct exynos7420_clk_top0_priv {
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struct exynos7420_clk_cmu_top0 *top0;
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unsigned long mout_top0_bus0_pll_half;
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unsigned long sclk_uart2;
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};
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static ulong exynos7420_topc_get_rate(struct clk *clk)
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{
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struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case DOUT_SCLK_BUS0_PLL:
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case SCLK_BUS0_PLL_A:
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case SCLK_BUS0_PLL_B:
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return priv->sclk_bus0_pll_a;
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case DOUT_SCLK_BUS1_PLL:
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case SCLK_BUS1_PLL_A:
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case SCLK_BUS1_PLL_B:
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return priv->sclk_bus1_pll_a;
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default:
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return 0;
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}
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}
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static struct clk_ops exynos7420_clk_topc_ops = {
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.get_rate = exynos7420_topc_get_rate,
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};
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static int exynos7420_clk_topc_probe(struct udevice *dev)
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{
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struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
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struct exynos7420_clk_cmu_topc *topc;
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struct clk in_clk;
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unsigned long rate;
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fdt_addr_t base;
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int ret;
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base = dev_get_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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topc = (struct exynos7420_clk_cmu_topc *)base;
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priv->topc = topc;
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ret = clk_get_by_index(dev, 0, &in_clk);
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if (ret >= 0)
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priv->fin_freq = clk_get_rate(&in_clk);
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rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
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if (readl(&topc->mux_sel[1]) & (1 << 16))
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rate >>= 1;
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rate /= DIVIDER(&topc->div[3], 0, 0xf);
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priv->sclk_bus0_pll_a = rate;
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rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
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DIVIDER(&topc->div[3], 8, 0xf);
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priv->sclk_bus1_pll_a = rate;
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return 0;
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}
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static ulong exynos7420_top0_get_rate(struct clk *clk)
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{
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struct exynos7420_clk_top0_priv *priv = dev_get_priv(clk->dev);
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struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
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switch (clk->id) {
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case CLK_SCLK_UART2:
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return priv->mout_top0_bus0_pll_half /
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DIVIDER(&top0->div_peric[3], 8, 0xf);
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default:
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return 0;
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}
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}
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static struct clk_ops exynos7420_clk_top0_ops = {
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.get_rate = exynos7420_top0_get_rate,
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};
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static int exynos7420_clk_top0_probe(struct udevice *dev)
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{
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struct exynos7420_clk_top0_priv *priv;
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struct exynos7420_clk_cmu_top0 *top0;
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struct clk in_clk;
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fdt_addr_t base;
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int ret;
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priv = dev_get_priv(dev);
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if (!priv)
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return -EINVAL;
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base = dev_get_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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top0 = (struct exynos7420_clk_cmu_top0 *)base;
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priv->top0 = top0;
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ret = clk_get_by_index(dev, 1, &in_clk);
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if (ret >= 0) {
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priv->mout_top0_bus0_pll_half =
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clk_get_rate(&in_clk);
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if (readl(&top0->mux_sel[1]) & (1 << 16))
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priv->mout_top0_bus0_pll_half >>= 1;
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}
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return 0;
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}
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static ulong exynos7420_peric1_get_rate(struct clk *clk)
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{
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struct clk in_clk;
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unsigned int ret;
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unsigned long freq = 0;
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switch (clk->id) {
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case SCLK_UART2:
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ret = clk_get_by_index(clk->dev, 3, &in_clk);
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if (ret < 0)
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return ret;
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freq = clk_get_rate(&in_clk);
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break;
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}
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return freq;
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}
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static struct clk_ops exynos7420_clk_peric1_ops = {
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.get_rate = exynos7420_peric1_get_rate,
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};
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static const struct udevice_id exynos7420_clk_topc_compat[] = {
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{ .compatible = "samsung,exynos7-clock-topc" },
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{ }
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};
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U_BOOT_DRIVER(exynos7420_clk_topc) = {
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.name = "exynos7420-clock-topc",
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.id = UCLASS_CLK,
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.of_match = exynos7420_clk_topc_compat,
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.probe = exynos7420_clk_topc_probe,
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.priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
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.ops = &exynos7420_clk_topc_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static const struct udevice_id exynos7420_clk_top0_compat[] = {
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{ .compatible = "samsung,exynos7-clock-top0" },
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{ }
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};
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U_BOOT_DRIVER(exynos7420_clk_top0) = {
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.name = "exynos7420-clock-top0",
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.id = UCLASS_CLK,
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.of_match = exynos7420_clk_top0_compat,
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.probe = exynos7420_clk_top0_probe,
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.priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
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.ops = &exynos7420_clk_top0_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static const struct udevice_id exynos7420_clk_peric1_compat[] = {
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{ .compatible = "samsung,exynos7-clock-peric1" },
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{ }
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};
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U_BOOT_DRIVER(exynos7420_clk_peric1) = {
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.name = "exynos7420-clock-peric1",
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.id = UCLASS_CLK,
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.of_match = exynos7420_clk_peric1_compat,
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.ops = &exynos7420_clk_peric1_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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