mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
378 lines
16 KiB
C
378 lines
16 KiB
C
/*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_ALPR 1 /* Board is ebony */
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#define CONFIG_440GX 1 /* Specifc GX support */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */
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#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
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#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
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#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
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#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
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#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CONFIG_CONS_INDEX 2 /* Use UART1 */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
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#undef CONFIG_SDRAM_ECC /* enable ECC support */
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#define CONFIG_SYS_SDRAM_TABLE { \
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{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
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{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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/*-----------------------------------------------------------------------
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* I2C EEPROM (PCF8594C)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
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/* 8 byte page write mode using */
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/* last 3 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run kernelx\" to boot the system;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth3\0" \
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"hostname=alpr\0" \
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"fdt_file=alpr/alpr.dtb\0" \
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"fdt_addr=400000\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath} ${init}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
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"mem=193M\0" \
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"net_nfs_fdt=tftp 200000 ${bootfile};" \
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"tftp ${fdt_addr} ${fdt_file};" \
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"run nfsargs addip addtty;" \
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"bootm 200000 - ${fdt_addr}\0" \
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"rootpath=/opt/projects/alpr/nfs_root\0" \
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"bootfile=/alpr/uImage\0" \
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"kernel_addr=fff00000\0" \
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"ramdisk_addr=fff10000\0" \
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"load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
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"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
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"cp.b 100000 fffc0000 40000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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"ethprime=ppc_4xx_eth3\0" \
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"ethact=ppc_4xx_eth3\0" \
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"autoload=no\0" \
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"ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
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"load_fpga=fpga load 0 ffe00000 10dd9a\0" \
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"mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
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"rootfstype=jffs2 init=/sbin/init\0" \
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"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
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";bootm 200000\0" \
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"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
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"addtty;bootm 200000\0" \
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"kernel1=setenv actkernel 'kernel1';run load_fpga " \
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"kernel1_mtd\0" \
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"kernel2=setenv actkernel 'kernel2';run load_fpga " \
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"kernel2_mtd\0" \
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""
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#define CONFIG_BOOTCOMMAND "run kernel2"
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#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
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#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
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#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
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#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_HAS_ETH3
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_FPGA
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#define CONFIG_CMD_I2C
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#undef CONFIG_CMD_LOADB
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#undef CONFIG_CMD_LOADS
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
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#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
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/* Board-specific PCI */
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#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
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#define CONFIG_SYS_PCI_MASTER_INIT
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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/*-----------------------------------------------------------------------
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* FPGA stuff
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*-----------------------------------------------------------------------*/
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#define CONFIG_FPGA
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#define CONFIG_FPGA_ALTERA
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#define CONFIG_FPGA_CYCLON2
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#define CONFIG_SYS_FPGA_CHECK_CTRLC
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#define CONFIG_SYS_FPGA_PROG_FEEDBACK
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#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
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Reihe geschaltet -> sollte gehen,
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aufpassen mit Datasize ist jetzt
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halt doppelt so gross ... Seite 306
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ist das mit den multiple Device in PS
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Mode erklaert ...*/
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/* FPGA program pin configuration */
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#define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
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#define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */
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#define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
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#define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
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#define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
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#define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */
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#define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */
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#define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */
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/*-----------------------------------------------------------------------
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* Definitions for GPIO setup
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*-----------------------------------------------------------------------*/
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#define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6)
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#define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9)
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#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26)
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#define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14)
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#define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15)
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/*-----------------------------------------------------------------------
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* NAND-FLASH stuff
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*-----------------------------------------------------------------------*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 4
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#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
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CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
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#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
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/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x92015480
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#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
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/* Memory Bank 1 (NAND-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */
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#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#endif /* __CONFIG_H */
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