mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
307 lines
9.7 KiB
C
307 lines
9.7 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8240 1
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#define CONFIG_PN62 1
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_CONS_INDEX 1
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_BSP
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_SAVEENV
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#undef CONFIG_CMD_SOURCE
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#define CONFIG_BAUDRATE 19200 /* console baudrate */
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#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#define CONFIG_SERVERIP 10.0.0.201
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#define CONFIG_IPADDR 10.0.0.200
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#define CONFIG_ROOTPATH /opt/eldk/ppc_82xx
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#define CONFIG_NETMASK 255.255.255.0
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#undef CONFIG_BOOTARGS
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#if 0
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/* Boot Linux with NFS root filesystem */
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#define CONFIG_BOOTCOMMAND \
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"setenv verify y;" \
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"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
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"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
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"loadp 100000; bootm"
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/* "tftpboot 100000 uImage; bootm" */
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#else
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/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
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#define CONFIG_BOOTCOMMAND \
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"setenv verify n;" \
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"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
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"root=/dev/ram rw " \
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"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
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"loadp 200000; bootm"
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
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#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */
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#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
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/*
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* PCI stuff
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* we need Plug 'n Play */
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#if 0
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#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */
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#endif
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/*
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* Networking stuff
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*/
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */
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#define CONFIG_PCNET_79C973
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#define _IO_BASE 0xfe000000 /* points to PCI I/O space */
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
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#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
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#undef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_MONITOR_LEN 0x00030000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_END 0x1000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
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#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
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#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */
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/*
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* Serial port configuration
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*/
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 1843200
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#define CONFIG_SYS_NS16550_COM1 0xff800008
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#define CONFIG_SYS_NS16550_COM2 0xff800000
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
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#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
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/* MCCR1 */
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#define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */
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#define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */
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/* MCCR2 */
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#define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */
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#define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */
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#define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */
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/* MCCR3 */
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#define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */
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#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
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#define CONFIG_SYS_RDLAT 3 /* data latency from read command */
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/* MCCR4 */
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#define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */
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#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
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#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
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#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
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#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */
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#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
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#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
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/* Memory bank settings:
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*
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* only bits 20-29 are actually used from these vales to set the
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* start/qend address the upper two bits will be 0, and the lower 20
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* bits will be set to 0x00000 for a start address, or 0xfffff for an
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* end address
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*/
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#define CONFIG_SYS_BANK0_START 0x00000000
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#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
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#define CONFIG_SYS_BANK0_ENABLE 1
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#define CONFIG_SYS_BANK1_START 0x00000000
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#define CONFIG_SYS_BANK1_END 0x00000000
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#define CONFIG_SYS_BANK1_ENABLE 0
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#define CONFIG_SYS_BANK2_START 0x00000000
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#define CONFIG_SYS_BANK2_END 0x00000000
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#define CONFIG_SYS_BANK2_ENABLE 0
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#define CONFIG_SYS_BANK3_START 0x00000000
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#define CONFIG_SYS_BANK3_END 0x00000000
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#define CONFIG_SYS_BANK3_ENABLE 0
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#define CONFIG_SYS_BANK4_START 0x00000000
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#define CONFIG_SYS_BANK4_END 0x00000000
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#define CONFIG_SYS_BANK4_ENABLE 0
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#define CONFIG_SYS_BANK5_START 0x00000000
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#define CONFIG_SYS_BANK5_END 0x00000000
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#define CONFIG_SYS_BANK5_ENABLE 0
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#define CONFIG_SYS_BANK6_START 0x00000000
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#define CONFIG_SYS_BANK6_END 0x00000000
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#define CONFIG_SYS_BANK6_ENABLE 0
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#define CONFIG_SYS_BANK7_START 0x00000000
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#define CONFIG_SYS_BANK7_END 0x00000000
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#define CONFIG_SYS_BANK7_ENABLE 0
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/*
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* Memory bank enable bitmask, specifying which of the banks defined above
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* are actually present. MSB is for bank #7, LSB is for bank #0.
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*/
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#define CONFIG_SYS_BANK_ENABLE 0x01
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#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
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/* see 8240 book for bit definitions */
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#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
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/* currently accessed page in memory */
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/* see 8240 book for details */
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/* SDRAM 0 - 256MB */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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/* PCI memory space */
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#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/* Config addrs, etc */
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#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#endif /* __CONFIG_H */
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