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https://github.com/brain-hackers/u-boot-brain
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02cd449f0b
This patch rewrites the mtmips architecture with the following changes: 1. Move MT7628 soc parts into a subfolder. 2. Lock parts of D-Cache as temporary stack. 3. Reimplement DDR initialization in C language. 4. Reimplement DDR calibration in a clear logic. 5. Add full support for auto size detection for DDR1 and DDR2. 6. Use accurate CPU clock depending on the input xtal frequency for timer and delay functions. Note: print_cpuinfo() has incompatible parts with MT7620 so it's moved into mt7628 subfolder. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
47 lines
995 B
C
47 lines
995 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
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#endif
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return 0;
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}
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int last_stage_init(void)
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{
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void *src, *dst;
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src = malloc(SZ_64K);
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dst = malloc(SZ_64K);
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if (!src || !dst) {
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printf("Can't allocate buffer for cache cleanup copy!\n");
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return 0;
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}
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/*
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* It has been noticed, that sometimes the d-cache is not in a
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* "clean-state" when U-Boot is running on MT7688. This was
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* detected when using the ethernet driver (which uses d-cache)
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* and a TFTP command does not complete. Copying an area of 64KiB
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* in DDR at a very late bootup time in U-Boot, directly before
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* calling into the prompt, seems to fix this issue.
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*/
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memcpy(dst, src, SZ_64K);
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free(src);
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free(dst);
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return 0;
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}
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