mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
02c2de6eb0
If the MAC address specified on the EEPROM is invalid (multicast or zero address), then u-boot fails to boot. Having a bad MAC address in the EEPROM should not prevent the system from booting. This commit changes the error path to just print an error messages in case of bad MAC address. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
374 lines
8.3 KiB
C
374 lines
8.3 KiB
C
/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on da850evm.c. Original Copyrights follow:
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*
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* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <net.h>
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#include <netdev.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <asm/arch/hardware.h>
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#include <asm/ti-common/davinci_nand.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/davinci_misc.h>
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#ifdef CONFIG_DAVINCI_MMC
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#include <mmc.h>
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#include <asm/arch/sdmmc_defs.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
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#ifdef CONFIG_DAVINCI_MMC
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/* MMC0 pin muxer settings */
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const struct pinmux_config mmc0_pins[] = {
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/* GP0[11] is required for SD to work on Rev 3 EVMs */
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{ pinmux(0), 8, 4 }, /* GP0[11] */
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{ pinmux(10), 2, 0 }, /* MMCSD0_CLK */
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{ pinmux(10), 2, 1 }, /* MMCSD0_CMD */
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{ pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
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{ pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
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{ pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
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{ pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
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/* LCDK supports only 4-bit mode, remaining pins are not configured */
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};
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#endif
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/* UART pin muxer settings */
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static const struct pinmux_config uart_pins[] = {
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{ pinmux(0), 4, 6 },
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{ pinmux(0), 4, 7 },
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{ pinmux(4), 2, 4 },
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{ pinmux(4), 2, 5 }
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};
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#ifdef CONFIG_DRIVER_TI_EMAC
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static const struct pinmux_config emac_pins[] = {
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{ pinmux(2), 8, 1 },
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{ pinmux(2), 8, 2 },
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{ pinmux(2), 8, 3 },
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{ pinmux(2), 8, 4 },
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{ pinmux(2), 8, 5 },
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{ pinmux(2), 8, 6 },
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{ pinmux(2), 8, 7 },
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{ pinmux(3), 8, 0 },
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{ pinmux(3), 8, 1 },
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{ pinmux(3), 8, 2 },
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{ pinmux(3), 8, 3 },
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{ pinmux(3), 8, 4 },
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{ pinmux(3), 8, 5 },
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{ pinmux(3), 8, 6 },
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{ pinmux(3), 8, 7 },
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{ pinmux(4), 8, 0 },
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{ pinmux(4), 8, 1 }
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};
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#endif /* CONFIG_DRIVER_TI_EMAC */
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/* I2C pin muxer settings */
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static const struct pinmux_config i2c_pins[] = {
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{ pinmux(4), 2, 2 },
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{ pinmux(4), 2, 3 }
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};
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#ifdef CONFIG_NAND_DAVINCI
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const struct pinmux_config nand_pins[] = {
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{ pinmux(7), 1, 1 },
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{ pinmux(7), 1, 2 },
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{ pinmux(7), 1, 4 },
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{ pinmux(7), 1, 5 },
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{ pinmux(8), 1, 0 },
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{ pinmux(8), 1, 1 },
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{ pinmux(8), 1, 2 },
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{ pinmux(8), 1, 3 },
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{ pinmux(8), 1, 4 },
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{ pinmux(8), 1, 5 },
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{ pinmux(8), 1, 6 },
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{ pinmux(8), 1, 7 },
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{ pinmux(9), 1, 0 },
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{ pinmux(9), 1, 1 },
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{ pinmux(9), 1, 2 },
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{ pinmux(9), 1, 3 },
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{ pinmux(9), 1, 4 },
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{ pinmux(9), 1, 5 },
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{ pinmux(9), 1, 6 },
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{ pinmux(9), 1, 7 },
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{ pinmux(12), 1, 5 },
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{ pinmux(12), 1, 6 }
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};
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#endif
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
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#define HAS_RMII 1
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#else
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#define HAS_RMII 0
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#endif
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const struct pinmux_resource pinmuxes[] = {
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PINMUX_ITEM(uart_pins),
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PINMUX_ITEM(i2c_pins),
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#ifdef CONFIG_NAND_DAVINCI
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PINMUX_ITEM(nand_pins),
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#endif
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};
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const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
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const struct lpsc_resource lpsc[] = {
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{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
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{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */
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{ DAVINCI_LPSC_EMAC }, /* image download */
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{ DAVINCI_LPSC_UART2 }, /* console */
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{ DAVINCI_LPSC_GPIO },
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#ifdef CONFIG_DAVINCI_MMC
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{ DAVINCI_LPSC_MMC_SD },
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#endif
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};
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const int lpsc_size = ARRAY_SIZE(lpsc);
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#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
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#define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
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#endif
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/*
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* get_board_rev() - setup to pass kernel board revision information
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* Returns:
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* bit[0-3] Maximum cpu clock rate supported by onboard SoC
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* 0000b - 300 MHz
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* 0001b - 372 MHz
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* 0010b - 408 MHz
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* 0011b - 456 MHz
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*/
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u32 get_board_rev(void)
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{
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return 0;
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}
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int board_early_init_f(void)
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{
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/*
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* Power on required peripherals
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* ARM does not have access by default to PSC0 and PSC1
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* assuming here that the DSP bootloader has set the IOPU
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* such that PSC access is available to ARM
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*/
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if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
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return 1;
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return 0;
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}
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int board_init(void)
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{
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#ifndef CONFIG_USE_IRQ
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irq_init();
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#endif
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* setup the SUSPSRC for ARM to control emulation suspend */
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writel(readl(&davinci_syscfg_regs->suspsrc) &
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~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
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DAVINCI_SYSCFG_SUSPSRC_UART2),
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&davinci_syscfg_regs->suspsrc);
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/* configure pinmux settings */
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if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
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return 1;
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#ifdef CONFIG_NAND_DAVINCI
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/*
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* NAND CS setup - cycle counts based on da850evm NAND timings in the
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* Linux kernel @ 25MHz EMIFA
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*/
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writel((DAVINCI_ABCR_WSETUP(15) |
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DAVINCI_ABCR_WSTROBE(63) |
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DAVINCI_ABCR_WHOLD(7) |
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DAVINCI_ABCR_RSETUP(15) |
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DAVINCI_ABCR_RSTROBE(63) |
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DAVINCI_ABCR_RHOLD(7) |
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DAVINCI_ABCR_TA(3) |
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DAVINCI_ABCR_ASIZE_16BIT),
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&davinci_emif_regs->ab2cr); /* CS3 */
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#endif
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#ifdef CONFIG_DAVINCI_MMC
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if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
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return 1;
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#endif
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#ifdef CONFIG_DRIVER_TI_EMAC
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if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
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return 1;
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davinci_emac_mii_mode_sel(HAS_RMII);
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#endif /* CONFIG_DRIVER_TI_EMAC */
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/* enable the console UART */
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writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
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DAVINCI_UART_PWREMU_MGMT_UTRST),
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&davinci_uart2_ctrl_regs->pwremu_mgmt);
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_EMAC
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/*
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* Initializes on-board ethernet controllers.
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*/
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int board_eth_init(bd_t *bis)
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{
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if (!davinci_emac_initialize()) {
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printf("Error: Ethernet init failed!\n");
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return -1;
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}
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return 0;
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}
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#endif /* CONFIG_DRIVER_TI_EMAC */
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#define CFG_MAC_ADDR_SPI_BUS 0
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#define CFG_MAC_ADDR_SPI_CS 0
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#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
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#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
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static int get_mac_addr(u8 *addr)
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{
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/* Need to find a way to get MAC ADDRESS */
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return 0;
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}
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void dsp_lpsc_on(unsigned domain, unsigned int id)
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{
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dv_reg_p mdstat, mdctl, ptstat, ptcmd;
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struct davinci_psc_regs *psc_regs;
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psc_regs = davinci_psc0_regs;
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mdstat = &psc_regs->psc0.mdstat[id];
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mdctl = &psc_regs->psc0.mdctl[id];
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ptstat = &psc_regs->ptstat;
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ptcmd = &psc_regs->ptcmd;
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while (*ptstat & (0x1 << domain))
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;
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if ((*mdstat & 0x1f) == 0x03)
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return; /* Already on and enabled */
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*mdctl |= 0x03;
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*ptcmd = 0x1 << domain;
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while (*ptstat & (0x1 << domain))
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;
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while ((*mdstat & 0x1f) != 0x03)
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; /* Probably an overkill... */
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}
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static void dspwake(void)
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{
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unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
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/* if the device is ARM only, return */
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if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
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return;
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if (!strcmp(getenv("dspwake"), "no"))
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return;
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*resetvect++ = 0x1E000; /* DSP Idle */
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/* clear out the next 10 words as NOP */
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memset(resetvect, 0, sizeof(unsigned) * 10);
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/* setup the DSP reset vector */
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REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
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dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
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REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
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}
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
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/**
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* rmii_hw_init
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*
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*/
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int rmii_hw_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
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int misc_init_r(void)
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{
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uint8_t tmp[20], addr[10];
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if (getenv("ethaddr") == NULL) {
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/* Read Ethernet MAC address from EEPROM */
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if (dvevm_read_mac_address(addr)) {
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/* Set Ethernet MAC address from EEPROM */
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davinci_sync_env_enetaddr(addr);
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} else {
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get_mac_addr(addr);
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}
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if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
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sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
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addr[0], addr[1], addr[2], addr[3], addr[4],
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addr[5]);
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setenv("ethaddr", (char *)tmp);
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} else {
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printf("Invalid MAC address read.\n");
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}
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}
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
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/* Select RMII fucntion through the expander */
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if (rmii_hw_init())
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printf("RMII hardware init failed!!!\n");
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#endif
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dspwake();
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return 0;
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}
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#ifdef CONFIG_DAVINCI_MMC
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static struct davinci_mmc mmc_sd0 = {
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.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
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.host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
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.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
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.version = MMC_CTLR_VERSION_2,
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};
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int board_mmc_init(bd_t *bis)
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{
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mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
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/* Add slot-0 to mmc subsystem */
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return davinci_mmc_init(bis, &mmc_sd0);
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}
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#endif
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