mirror of
https://github.com/brain-hackers/u-boot-brain
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56519c4f04
Some systems have so much RAM that the end of RAM is beyond 4GB. An example would be a Tegra124 system (where RAM starts at 2GB physical) that has more than 2GB of RAM. In this case, we want gd->ram_size to represent the actual RAM size, so that the actual RAM size is passed to the OS. This is useful if the OS implements LPAE, and can actually use the "extra" RAM. However, we can't use get_ram_size() to verify the actual amount of RAM present on such systems, since some of the RAM can't be accesses, which confuses that function. Avoid calling get_ram_size() when the RAM size is too large for it to work correctly. It's never actually needed anyway, since there's no reason for the BCT to report the wrong RAM size. In systems with >=4GB RAM, we still need to clip the reported RAM size since U-Boot uses a 32-bit variable to represent the RAM size in bytes. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
181 lines
3.8 KiB
C
181 lines
3.8 KiB
C
/*
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* (C) Copyright 2010-2014
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/mc.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/sys_proto.h>
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#include <asm/arch-tegra/warmboot.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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/* UARTs which we can enable */
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UARTA = 1 << 0,
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UARTB = 1 << 1,
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UARTC = 1 << 2,
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UARTD = 1 << 3,
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UARTE = 1 << 4,
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UART_COUNT = 5,
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};
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/* Read the RAM size directly from the memory controller */
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unsigned int query_sdram_size(void)
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{
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struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
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u32 emem_cfg, size_bytes;
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emem_cfg = readl(&mc->mc_emem_cfg);
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#if defined(CONFIG_TEGRA20)
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debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
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size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
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#else
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debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
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/*
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* If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
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* and will wrap. Clip the reported size to the maximum that a 32-bit
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* variable can represent (rounded to a page).
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*/
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if (emem_cfg >= 4096) {
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size_bytes = U32_MAX & ~(0x1000 - 1);
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} else {
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/* RAM size EMC is programmed to. */
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size_bytes = emem_cfg * 1024 * 1024;
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/*
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* If all RAM fits within 32-bits, it can be accessed without
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* LPAE, so go test the RAM size. Otherwise, we can't access
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* all the RAM, and get_ram_size() would get confused, so
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* avoid using it. There's no reason we should need this
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* validation step anyway.
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*/
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if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
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size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
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size_bytes);
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}
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#endif
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#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
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/* External memory limited to 2047 MB due to IROM/HI-VEC */
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if (size_bytes == SZ_2G)
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size_bytes -= SZ_1M;
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#endif
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return size_bytes;
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}
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int dram_init(void)
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{
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/* We do not initialise DRAM here. We just query the size */
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gd->ram_size = query_sdram_size();
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return 0;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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printf("Board: %s\n", sysinfo.board_string);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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static int uart_configs[] = {
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#if defined(CONFIG_TEGRA20)
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#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
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FUNCMUX_UART1_UAA_UAB,
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#elif defined(CONFIG_TEGRA_UARTA_GPU)
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FUNCMUX_UART1_GPU,
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#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
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FUNCMUX_UART1_SDIO1,
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#else
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FUNCMUX_UART1_IRRX_IRTX,
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#endif
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FUNCMUX_UART2_UAD,
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-1,
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FUNCMUX_UART4_GMC,
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-1,
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#elif defined(CONFIG_TEGRA30)
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FUNCMUX_UART1_ULPI, /* UARTA */
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-1,
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-1,
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-1,
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-1,
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#elif defined(CONFIG_TEGRA114)
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-1,
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-1,
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-1,
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FUNCMUX_UART4_GMI, /* UARTD */
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-1,
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#else /* Tegra124 */
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FUNCMUX_UART1_KBC, /* UARTA */
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-1,
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-1,
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FUNCMUX_UART4_GPIO, /* UARTD */
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-1,
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#endif
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};
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/**
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* Set up the specified uarts
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*
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* @param uarts_ids Mask containing UARTs to init (UARTx)
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*/
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static void setup_uarts(int uart_ids)
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{
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static enum periph_id id_for_uart[] = {
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PERIPH_ID_UART1,
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PERIPH_ID_UART2,
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PERIPH_ID_UART3,
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PERIPH_ID_UART4,
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PERIPH_ID_UART5,
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};
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size_t i;
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for (i = 0; i < UART_COUNT; i++) {
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if (uart_ids & (1 << i)) {
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enum periph_id id = id_for_uart[i];
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funcmux_select(id, uart_configs[i]);
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clock_ll_start_uart(id);
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}
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}
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}
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void board_init_uart_f(void)
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{
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int uart_ids = 0; /* bit mask of which UART ids to enable */
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#ifdef CONFIG_TEGRA_ENABLE_UARTA
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uart_ids |= UARTA;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTB
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uart_ids |= UARTB;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTC
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uart_ids |= UARTC;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTD
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uart_ids |= UARTD;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTE
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uart_ids |= UARTE;
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#endif
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setup_uarts(uart_ids);
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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